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| Scroll Title |
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| anchor | Table_SIP_B2B |
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| title | General PL I/O to B2B connectors information |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
|---|
| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FPGA Bank | Type | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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| 13 | HR | J1 | 48(24) | VCCO_13 | variable from carrier | | 500 | - | J1 | 4 | 3.3V |
| | 501 | - | J2 | 37 | VMIO1 | variable from carrier | | 33 | HR | J3 | 34 | 3.3V |
| | 35 | HR | J3 | 20 | 3.3V |
| | 35 | HR | J2 | 22 | 3.3V |
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JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.
| Scroll Title |
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| anchor | Table_SIP_JTGB2B |
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| title | JTAG pins connectionGeneral PL I/O to B2B connectors information |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
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| cellHighlighting | true |
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|
JTAG Signal Pin| TMS | J2-12 | | TDI | J2-10 | | TDO | J2-8 | | TCK | J2-6 | |
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| Connector | I/O Signal Count | Voltage Level | Notes |
|---|
| 13 | J1 | 48(24) | VCCO_13 | variable from carrier | | 500 | J1 | 4 | 3.3V |
| | 501 | J2 | 37 | VMIO1 | variable from carrier | | 33 | J3 | 34 | 3.3V |
| | 35 | J3 | 20 | 3.3V |
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JTAG Interface
JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.
| Scroll Title |
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| anchor | Table_OBPSIP_MIOsJTG |
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| title | MIOs JTAG pins connection |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
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MIO Schematic| TMS | J2-12 | | TDI | J2-10 | | TDO | J2-8 | | TCK | J2-6 |
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MIO Pins
| Scroll Title |
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| anchor | Table_OBP_MIOs |
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| title | MIOs pins |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
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| MIO Pin | Schematic | Notes |
|---|
| Notes | MIO0 | MIO0 | RTC interrupt |
|---|
| MIO1 | SPI_CS | SPI Flash | | MIO2-5 | SPI_DQ0-3/M0-3 | SPI Flash | | MIO6 | SPI_SCK/M4 | SPI Flash clock | | MIO7 | LED RED | LED | | MIO8 | D | CAN Transceiver | | MIO9 | R | CAN Transceiver | | MIO10 | IO_0 | J1-7 | | MIO11 | IO_1 | J1-9 | | MIO12 | IO_2 | J1-11 | | MIO13 | IO_3 | J1-13 | | MIO14 | SCL | EEPROM | | MIO15 | SDA | EEPROM | | MIO16-MIO53 | PS_MIOxx |
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The RTC has an I2C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy.RTC intruppt is connected to MIO0 connected to Bank 500, pin G6.. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy.
RTC intruppt is connected to MIO0 connected to Bank 500 through pin G6.
| Scroll Title |
|---|
| anchor | Table_OBP_RTC |
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| title | I2C interface MIOs and pins |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
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| MIO Pin | Schematic | Pin | Notes |
|---|
| MIO15 | SDA | U7-5 | On-board RTC, and EEPROM | | MIO14 | SCL | U7-4 | On-board RTC, and EEPROM |
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| Scroll Title |
|---|
| anchor | Table_OBP_RTC_Add |
|---|
| title | I2C interface MIOs and pinsAddress |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
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| MIO Pin | Schematic | PinMIO15SDAOn-board RTC, and MIO14 | SCL | U7-4 | On-board RTC, and EEPROM |
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EEPROM
The Microchip Technology Inc. 24xx64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. The 24xx64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.
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