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| Scroll Title |
|---|
| anchor | Table_SIP_JTG |
|---|
| title | JTAG pins connection |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
JTAG Signal | B2B Pin |
|---|
| TMS | JM2J2-12 | | TDI | JM2J2-10 | | TDO | JM2J2-8 | | TCK | JM2J2-6 |
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MIO Pins
| Scroll Title |
|---|
| anchor | Table_OBP_MIOs |
|---|
| title | MIOs pins |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| MIO Pin | Schematic | Notes |
|---|
| MIO0 | MIO0 | RTC interrupt | | MIO1 | SPI_CS | SPI Flash | | MIO2-5 | SPI_DQ0-3/M0-3 | SPI Flash | | MIO6 | SPI_SCK/M4 | SPI Flash clock | | MIO7 | LED RED | LED | | MIO8 | D | CAN Transceiver | | MIO9 | R | CAN Transceiver | | MIO10 | IO_0 | JM1J1-7 | | MIO11 | IO_1 | JM1J1-9 | | MIO12 | IO_2 | JM1J1-11 | | MIO13 | IO_3 | JM1J1-13 | | MIO14 | SCL | EEPROM | | MIO15 | SDA | EEPROM | | MIO16-MIO53 | PS_MIOxx |
|
UART
There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to PL pins.
Recommended mapping for primary (console, debug) UART are MIO52, MIO53.
On-board Peripherals
| Page properties |
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
|
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| Scroll Title |
|---|
| anchor | Table_PWR_BV |
|---|
| title | Zynq SoC bank voltages. |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Schematic Name | | HR I/O Bank | Notes |
|---|
| 500 | VCCO_MIO0_500 | 3.3V | Supported |
| | 501 | VCCO_MIO1_500 | Variable |
|
| | 502 | VCCO_DDR_502 | 1.5V | Supported |
| | 13 HR | VCCO_13 | Variable |
| Supplied by the carrier board. J1 | | 33 HR | 3.3V | 3.3V | Supported | Supplied by carrier board. J3 | | 34 HR | 3.3V | 3.3V | Supported |
| | 35 HR | 3.3V | 3.3V | Supported | Supplied by the carrier board. J2, J3 |
|
Board to Board Connectors
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