Page History
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| Function | MGT Lane | Required Ref Clock | Clock Source | Comment |
|---|---|---|---|---|
| PCIe | PS 0 | 100 MHz | Si5345 CLK0 signal of prog. PLL on mounted SoM | clock signal routed on carrier board to PCIe connector J1 |
| USB3 | PS 1 | 100 MHz | Si5345 CLK4 signal of prog. PLL on mounted SoM | clock signal routed internally on-module, |
| SATA | PS 2 | 150 MHz | On-board oscillator U23 | optional: Si5345 CLK4 signal of prog. PLL on mounted SoM |
| DP.0 | PS 3 | 27 MHz | Si5345 CLK5 signal of prog. PLL on mounted SoM | DisplayPort GT SERDES clock signal, Si5345 CLK6 signal of prog. PLL on mounted SoM, |
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| Function | MGT Lane | Required Ref Clock | Clock Source | Comment |
|---|---|---|---|---|
| FireFly | B128 MGT Lanes 0..3 | - | Si5345 CLK6 signal of prog. PLL on mounted SoM | clock signal internally on-module routed to B128 |
| SFP | B230 MGT Lane 2 | 125 / 156.25 MHz | Si5345 CLK7 signal of prog. PLL on mounted SoM | clock signal routed on carrier board to B230 |
| SFP | B230 MGT Lane 3 | 125 / 156.25 MHz | Si5345 CLK7 signal of prog. PLL on mounted SoM | clock signal routed on carrier board to B230 |
Table 9: MGT Lane Assignment
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The TEBF0808 carrier board provides with its Mini-ITX form factor the possibility to encase the board in a PC Enclosure. For this purpose, the board is equipped with several Intel-PC compatible headers to connect them to the PC Enclosure.
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