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changes.mady.by.user John Hartfiel

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Comment: Corrected figure citation in text.

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The System Controller CPLDs will be programmed by the XMOD-Header J28 in a cascaded JTAG chain as visualized in Figure 89. To program the System Controller CPLDs, the JTAG interface of these devices have to be activated by DIP-switch S4-3.
The 4 GPIO/UART pins (XMOD1_A/B/E/G) of the XMOD-Header J28 are routed to the System Controller CPLD U17.

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Figure 13: Power-On Sequence Utilizing DCDC Converter Control Signals

Note

As shown in Figure 1213, the DIP switch S4-4 has to be closed if using only 12V single power supply through 12V power jack J25, otherwise the 5V voltage level will not be enabled to generate the 3V3SB voltage to power up the SC CPLD U39 and starting the power-on sequence.
By using an ATX-24 power connector on J20, there is usually also a 5V supply voltage provided, hence the DIP switch S4-4 is not relevant in this case of power supply.

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