Page History
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| DIP-switch S4 | Position ON | Position OFF | Notes |
|---|---|---|---|
| S4-1 | PUDC_B is Low | PUDC_B is HIGH | Internal pull-up resistors during configuration are enabled at ON-position. I/O's are 3-stated until configuration of the FPGA completes. |
| S4-2 | x | x | not connected |
| S4-3 | SC CPLDs' JTAG enabled | SC CPLDs' JTAG disabled | JTAG interface is enabled on both SC CPLDs, as this CPLDs are configured in a casdaced JTAG chain. |
| S4-4 | DC-DC converter U18 (5V) enabled | DC-DC converter U18 (5V) not manually enabled | In OFF-position, the DC-DC-converter will be still enabled by the control signals Enable-signal of SC CDPD U17 (wired-OR circuit). |
Table 20: DIP-switch S4 functionality description
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Absolute Maximum Ratings
Parameter | Min | Max | Unit | Notes / Reference Document | |||||
|---|---|---|---|---|---|---|---|---|---|
| PL_DCIN | -0.3 | 7 | V | TPS82085SIL / EN63A0QI data sheet | |||||
| DCDCIN | -0.3 | 7 | V | TPS82085SIL / TPS51206 data sheet | |||||
| LP_DCDC | -0.3 | 4 | V | TPS3106K33DBVR data sheet | |||||
| GT_DCDC | -0.3 | 7 | V | TPS82085SIL data sheet||||||
Storage temperature (ambient) | - 4055 | 10085 | °C ROHM Semiconductor SML-P11 Series data sheet | Marvell 88E1512 datasheet |
| Note |
|---|
| Assembly variants for higher storage temperature range are available on request. |
Recommended Operating Conditions
| Parameter | Min | Max | Unit | Notes / Reference Document | |||||
|---|---|---|---|---|---|---|---|---|---|
| PL_DCIN | 2.5 | 6 | V | EN63A0QI / TPS82085SIL data sheet | |||||
| DCDCIN | 3.1 | 6 | V | TPS82085SIL / TPS51206PSQ data sheet | |||||
| LP_DCDC | 2.5 | 3.6 | V | TPS82085SIL / TPS3106 data sheet
Operating Temperature Ranges
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