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Scroll Title |
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anchor | Table_SIP_B2B |
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title | General PL I/O to B2B connectors information |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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13 | J1 | 48(24) | VCCO_13 | variable from carrier | 500 | J1 | 4 | 3.3V |
| 501 | J2 | 37 | VMIO1 | variable from carrier | 33 | J3 | 34 | 3.3V |
| 35 | J3 | 20 | 3.3V |
| 35 | J2 | 22 | 3.3V |
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DDR3 SDRAM
The TE0728 SoM has two 512 MByte volatile DDR3 SDRAM IC for storing user application code and data.
Configuration of the DDR3 memory controller in the FPGA should be done using the MIG tool in the Xilinx Vivado Design Suite IP catalog.
Ethernet
There are two 100 MBit Extreme Temperature Ethernet provided by Texas Instrument on the board. Datasheet is provided at TI website. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz source is provided from MEMS Oscillator. There is no sharing of signals for the two PHY's.
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Scroll Title |
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anchor | Table_OBP_CAN |
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title | CAN Tranciever interface MIOs |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MIO Pin | Schematic | Pin | Notes |
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MIO8 | D | U16-1 | Driver Input | MIO9 | R | U16-4 | Reciever Output |
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Low Dropout Linear Regulator
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Clock Sources
Scroll Title |
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anchor | Table_OBP_CLK |
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title | Osillators |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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IC | Description | Frequency | Used as |
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U14 | MEMS Oscillator | 50 MHz | PS PLL clock | U5 | MEMS Oscillator | 25 MHz | Ethernet PHY Clock | U7 | RTC (internal oscillator) | 32.768 KHz | Used by RTC, CLKOUT of RTC not connected |
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