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* TBD - To Be Determined
Power on Sequence
The PS and PL power supplies are fully independent. The recommended power-on sequence is VCCPINT, VCCPAUX and VCCPLL together, then the PS VCCO supplies (VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. TE07028 SoM meets the recommended criteria to power up the Xilinx Zynq properly by keeping a specific sequence of enabling the on-board DC-DC converters and regulators dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages. When the U8 and U9 generates PWRGD signal, it turns on the U4 which generates PWRGD_3.3V, it turns on the U6 and it generates PWROK signal which is connected to MR. Whenever the supply voltage for U12 drops down below the threshold it resets the system. Actually it resets the system when all regulators are working.
| Scroll Title |
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| anchor | Figure_PWR_PS |
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| title | Power On Sequence |
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| | draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| diagramDisplayName | |
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| lbox | false |
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| revision | 6 |
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| diagramName | Figure_PWR_PS |
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| width | |
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| links | auto |
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The microprocessor supervisory circuits monitor system voltages asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. The RESET output remains low for the user adjustable delay time after the SENSE voltage and MR return above their thresholds. Datasheet is available in Texas Instruments website.
When the U8 and U9 generates PWRGD signal, it turns on the U4 which generates PWRGD_3.3V, it turns on the U6 and it generates PWROK signal which is connected to MR. Whenever the supply voltage for U12 drops down below the threshold it resets the system. Actually it resets the system when all regulators are working.
Power Rails
| Scroll Title |
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| anchor | Table_PWR_PR |
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| title | Module power rails. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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B2B Name | B2B JM1 Pin | B2B JM2 Pin | B2B JM3 Pin | Direction | Notes |
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| VIN | 1,3 | - | - | Input | Supply voltage from carrier board. | | VCCO_13 | 39 | - | - | I/O |
| | VBATT | - | 1 | - | Output | RTC Supply voltage | | 3.3V | 19 | 4 | 25,57 | Output | Internal 3.3V voltage level. | | VMIO | - | 2 |
| Input | 3.3V from carrier | 1.8V | - | 5 | - | Output | Internal 1.8V voltage level. |
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| Scroll Title |
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| anchor | Table_TS_AMR_PL |
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| title | PL absolute maximum ratings |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| Symbols | Description | Min | Max | Unit |
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| VCCINT | PL internal logic supply voltage | -0.5 | 1.1 | V | | VCCPAUX | PL auxiliary supply voltage | -0.5 | 2.0 | V | | VCCPLL | PL PLL supply | -0.5 | 1.1 | V | | VPREF | PL input reference voltage | -0.5 | 2.0 | V | | VCCO | PL supply voltage for HR I/O banks | -0.5 | 3.6 | V | | VIN | I/O input voltage for HR I/O banks | 1.71 | 3.45 | V |
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Recommended Operating
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Conditionse
| Scroll Title |
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| anchor | Table_TS_ROC |
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| title | Recommended operating conditions |
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| orientation | portrait |
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| sortDirection | ASC |
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| style | |
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| sortByColumn | 1 |
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| Parameter | Min | Max | Units | Reference Document |
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| VIN supply voltage | 3.5 | 60 | V | TPS54260-Q1 datasheets. | | Supply voltage for PS MIO banks | 1.71 | 3.465 | V | See Xilinx DS187 datasheet. | | I/O input voltage for PS MIO banks | -0.2 | VCCO_MIO + 0.20 | V | See Xilinx DS187 datasheet. | | Supply voltage for PS DDR | 1.14 | 1.89 | V | See Xilinx DS187 datasheet. | | I/O input voltage for PS DDR | -0.20 | VCCO_DDR + 0.20 | V | See Xilinx DS187 datasheet. | | Supply voltage for HR I/Os banks | 1.14 | 3.465 | V | See Xilinx DS187 datasheet. | | I/O input voltage for HR I/O banks | -0.20 | VCCIO + 0.20 | V | See Xilinx DS187 datasheet. | | Storage Temperature | -4540 | +125 | °C | See Xilinx DS187 datasheet. |
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Temprature Operating range: -40°C to +85°C105°C.
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
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