Page History

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MIO Pins

UART

There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to PL pins.

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Quad SPI Flash Memory

On-board QSPI flash memory is used to store initial FPGA configuration. Datasheet is provided in Texas Instruments. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

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RTC 

The RV-3029-C3 is an ultra miniature Real-Time-Clock Module with embedded Crystal. This RTC has an I²C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy of ± 6ppm from -40°C to +85°C and ± 8ppm from -40°C to +125°C.

RTC intruppt is connected to MIO0 connected to Bank 500, pin G6.

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DDR3 SDRAM

The TE0728 SoM has two 512 GByte MByte volatile DDR3 SDRAM IC for storing user application code and data.

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data.

 Configuration of the DDR3 memory controller in the FPGA should be done using the MIG tool in the Xilinx Vivado Design Suite IP catalog.

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There are two 100 MBit Extreme Temperature Ethernet  DP83848-EP are Ethernet provided by Texas Instrument on the board. Datasheet is provided TI website, Literature number SNLS208H. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz source is provided from MEMS Oscillator. There is no sharing of signals for the two PHY's.

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When connecting the PHY's to Zynq PS ETH0, ETH1 EMIO GMII Interfaces it is recommended to use GMII to MII Wrap IP Core. This IP core maps the EMIO GMII to external MII Interface.

CAN Transceiver

The SN65HVD230Q,  controller area network Controller Area Network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is avaiable available in Texas Instrumens website. They are intended for use in applications employing the CAN serial communication physical layer in accordance with the ISO 11898 standard. TI website. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps. Temperature must be in range of -40°C ~125°C . 

Low Quiescent Current Programmable Delay Supervisory Circuit

The TPS3808G01-Q1 microprocessor supervisory circuits monitor system voltages from 0.4 V to 5 V, asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. The RESET output remains low for the useradjustable user adjustable delay time after the SENSE voltage and MR return above their thresholds. Datasheet is available in Texas Instruments website.

The TPS3808G01-Q1 The  device uses a precision reference to achieve 0.5% threshold accuracy for VIT ≤ 3.3 V. The reset delay time can be set to 20 ms by disconnecting the CT pin, 300 ms by connecting the CT pin to VDD using a resistor, or can be useradjusted from 1.25 ms to 10 s by connecting the CT pin to an external capacitor. The TPS3808G01-Q1 device has a very low typical quiescent current of 2.4 μA, so it is well suited for battery-powered applications. 

Low Dropout Linear Regulator

The TPS74801-Q1 low-dropout (LDO)  provides an easy-to-use robust power management  solution for a wide variety of applications. User programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and well- suited for powering many different types of Monitoring or Provides a Sequencing Signal processors and ASICs. The enable input and power for Other Supplies good output allow easy sequencing with external regulators. This complete flexibility permits the user to configure a solution that meets the sequencing Voltage Startup requirements of FPGAs, DSPs, and other applications with special start-up requirements.

A precision reference and error amplifier deliver 2% accuracy over load, line, temperature, and process. The device is stable with any type of capacitor greater than or equal to 2.2 μF, and is fully specified SON-10 and 5 x 5 QFN-20 Packages from –40°C to 105°C for the DRC package, and from –40°C to 125°C for the RGW package.

Clock Sources

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Bank Voltages

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