Page History
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| Function | MGT Lane | Required Ref Clock | Clock Source | Comment |
|---|---|---|---|---|
| PCIe | PS 0 | 100 MHz | Si5345 CLK0 of prog. PLL on mounted SoM | wired clock signal routed on carrier board to PCIe connector J1 |
| USB3 | PS 1 | 100 MHz | Si5345 CLK4 of prog. PLL on mounted SoM | clock signal routed internally on-module wired, |
| SATA | PS 2 | 150 MHz | On-board oscillator U23 | optional: Si5345 CLK4 of prog. PLL on mounted SoM |
| DP.0 | PS 3 | 27 MHz | Si5345 CLK5 of prog. PLL on mounted SoM | DisplayPort GT SERDES Clock Si5345 CLK6 of prog. PLL on mounted SoM, |
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| Function | MGT Lane | Required Ref Clock | Clock Source | Comment |
|---|---|---|---|---|
| FireFly | B128 MGT Lanes 0..3 | - | Si5345 CLK6 of prog. PLL on mounted SoM | clock signal internally on-module wiredrouted |
| SFP | B230 MGT Lane 2 | 125 / 156.25 MHz | Si5345 CLK7 of prog. PLL on mounted SoM | wired clock signal routed on carrier board |
| SFP | B230 MGT Lane 3 | 125 / 156.25 MHz | Si5345 CLK7 of prog. PLL on mounted SoM | wired clock signal routed on carrier board |
Table 9: MGT Lane Assignment
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Figure 11: Clocking Configuration of TE0808 SoM on TEBF0808 Carrier Board
To configure the programmable PLL clock generator on the mounted TE0808 SoM, refer to the TRM of this SoM.
| Note |
|---|
Si5338 OTP ROM is not programmed by default at delivery, so it is customers responsibility to either configure Si5338 during FSBL or then use SiLabs programmer and burn the OTP ROM with customer fixed clock setup. |
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| Note |
|---|
Refer to the TE0808 TRM for the internal wiring routing of the on-module Si5345 10-channel PLL clock generator with signals to the clock input pins of the MGT banks. Also how to configure the programmable Si5345 PLL clock generator on the mounted TE0808 SoM. |
Oscillators
The TEBF0808 carrier board is equipped several on-board oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the on-board peripherals with reference clock-signals:
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Overview
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