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PS7 UART
There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to PL pins.
Recommended mapping for primary (console, debug) UART are MIO52, MIO53 for all cases when MIO1 is not used for off-board Gigabit ETH PHY.
Subsections...
On-board Peripherals
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| Designator | Color | Connected to | Active Level | IO Standard |
|---|---|---|---|---|
| D9 | Green | DONE | Low | not applicable |
| D8 | RED | MIO7 | High | not applicable |
| D4 | Green | PL pin V18 | High | LVCMOS33 |
512 Mbyte DDR3L SDRAM
Power and Power-On Sequence
Ethernet
There are two 100 MBit Extreme Temperature Ethernet PHY's DP83848YB on the board. Datasheet is available from TI, Literature number SNLS208H. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz source is provided from MEMS Oscillator. All LED outputs have on-board pull-ups. Outputs to Magnetics have also required termination resistors on board.
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When connecting the PHY's to Zynq PS ETH0, ETH1 EMIO GMII Interfaces it is recommended to use GMII to MII Wrap IP Core. This IP core maps the EMIO GMII to external MII Interface.
Power and Power-On Sequence
Power Consumption
Power Distribution Dependencies
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Overview
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