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The MGT-banks have also clock input-pins which are exposed to the FMC connector. Following MGT-lanes are available on the FMC connectors J5:

B2B

Type

Count of MGT Lanes

Schematic Names / Connector Pins

MGT Bank's Reference Clock Inputs from FMC Connector

J1GTH

4 GTH lanes

B228_RX3_P, B228_RX3_N, pins J5-A10, J5-A11
B228_TX3_P, B228_TX3_N, pins J5-A30, J5-A31

B228_RX2_P, B228_RX2_N, pins J5-A6, J5-A7
B228_TX2_P, B228_TX2_N, pins J5-A26, J5-A27

B228_RX1_P, B228_RX1_N, pins J5-A2, J5-A3
B228_TX1_P, B228_TX1_N, pins J5-A22, J5-A23

B228_RX0_P, B228_RX0_N, pins J5-C6, J5-C7
B228_TX0_P, B228_TX0_N, pins J5-C2, J5-C3

1 MGT clock (B228_CLK0) from FMC connector
J5 (pins J5-D4, J5-D5) to MPSoC's MGT bank

J1

GTH

4 GTH lanes

B229_RX3_P, B229_RX3_N, pins J5-B12, J5-B13
B229_TX3_P, B229_TX3_N, pins J5-B32, J5-B33

B229_RX2_P, B229_RX2_N, pins J5-B16, J5-B17
B229_TX2_P, B229_TX2_N, pins J5-B36, J5-B37

B229_RX1_P, B229_RX1_N, pins J5-A18, J5-A19
B229_TX1_P, B229_TX1_N, pins J5-A38, J5-A39

B229_RX0_P, B229_RX0_N, pins J5-A14, J5-A15
B229_TX0_P, B229_TX0_N, pins J5-A34, J5-A35

1 MGT clock (B229_CLK0) from FMC connector
J5 (pins J5-B20, J5-B21) to MPSoC's MGT bank

J1

GTH

2 GTH lanes

B230_RX1_P, B230_RX1_N, pins J5-B4, J5-B5
B230_TX1_P, B230_TX1_N, pins J5-B24, J5-B25

B230_RX0_P, B230_RX0_N, pins J5-B8, J5-B9
B230_TX0_P, B230_TX0_N, pins J5-B28, J5-B29

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Follwowing table contains a brief description of the control and status signals of PCIe interface:

Signal Schematic Name	FPGA Direction	Description	Logic
WAKE	Input	Link reactivation	Low active
PERST	Output	PCI Express reset input	Low active
PRSNT1	Input	Reference pin for PCIe Card lane size	-
PRSNT2	Input	PCI Express ×1 cards	connect to PRSNT1
PRSNT3	Input	PCI Express ×4 cards	connect to PRSNT1
PRSNT4	Input	PCI Express ×8 cards	connect to PRSNT1
PRSNT5	Input	PCI Express ×16 cards	connect to PRSNT1
PCIE_I²C	BiDir	2-wire PCIE System Management Bus	-

Table 10: Description of MGT Connectors Control and Status Signals

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Follwowing table contains a brief description of the control and status signals of the MGT lanes incorporating SFP+ and Samtec FireFly connectors:

Signal Schematic Name	Connector Type	FPGA Direction	Description	Logic
SFPx_TX_DISABLE	SFP+	Output	SFP Enabled / Disabled	Low active
SFPx_LOS	SFP+	Input	Loss of receiver signal	High active
SFPx_RS0	SFP+	Output	Full RX bandwidth	Low active
SFPx_RS1	SFP+	Output	Reduced RX bandwidth	Low active
SFPx_M-DEF0	SFP+	Input	Module present / not present	Low active
SFPx_TX_FAULT	SFP+	Input	Fault / Normal Operation	High active
SFPx_I²C	SFP+	BiDir	2-wire Serial Interface	-
FFx_MPRS	FireFly	Output	depending on connected module	-
FFx_MSEL	FireFly	Output	depending on connected module	-
FFx_INTL	FireFly	Input	Module interrupt line	-
FFx_RSTL	FireFly	Output	Module reset line	-
FFx_I²C	FireFly	BiDir	2-wire Serial Interface	-

Table 12: Description of MGT Connectors Control and Status Signals

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