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| DIP-switch S4 | Position ON | Position OFF | Notes |
|---|---|---|---|
| S4-1 | PUDC_B is Low | PUDC_B is HIGH | Internal pull-up resistors during configuration are enabled at ON-position., means I/O's are 3-stated until configuration of the FPGA completes. |
| S4-2 | x | x | not connected |
| S4-3 | SC CPLDs' JTAG enabled | SC CPLDs' JTAG disabled | JTAG interface is enabled on both SC CPLDs, as this CPLDs are configured in a casdaced JTAG chain. |
| S4-4 | DC-DC converter U18 (5V) enabled | DC-DC converter U18 (5V) not manually enabled | In OFF-position, the DC-DC-converter will be still enabled by the Enable-signal of SC CDPD U17 (wired-OR circuit). |
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The power-on sequence of the on-board DC-DC converters depens on the current firmware of the System Controller CPLD U17.
Following diagram visualizes the connection of the DC-DC converter control signals ('Enable', 'Power-Good') with System Controller CPLD U17, which enables the particular on-board voltages.
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