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On-board QSPI flash memory S25FL127SABMFV10 is used to store initial FPGA configuration. Datasheet is provided here. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
LEDLEDs
Designator | Color | Connected to | Active Level | IO Standard |
---|---|---|---|---|
D9 | Green | DONE | Low | not applicable |
D8 | RED | MIO7 | High | LVCMOS33 |
D4 | Green | PL pin V18 | High | LVCMOS33 |
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When connecting the PHY's to Zynq PS ETH0, ETH1 EMIO GMII Interfaces it is recommended to use GMII to MII Wrap IP Core. This IP core maps the EMIO GMII to external MII Interface.
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The SN65HVD230Q, controller area network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is avaiable in Texas Instrumens website. They are intended for use in applications employing the CAN serial communication physical layer in accordance with the ISO 11898 standard. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps. Temperature must be in range of -40C~125C.
IC | Description | Frequency | Used as |
---|---|---|---|
U14 | MEMS Oscillator | 33.3333 MHz | PS7 PLL clock |
U5 | MEMS Oscillator | 25 MHz | Ethernet PHY Clock |
U7 | RTC (internal oscillator) | 32.768 KHz | Used by RTC, CLKOUT of RTC not connected |
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