...
| Page properties |
|---|
|
Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
|
Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
...
| Scroll Title |
|---|
| anchor | Table_SIP_B2B |
|---|
| title | General PL I/O to B2B connectors information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
|---|
| 13 | JM1 | 48 | VCCO_13 |
| | 500 | JM1 | 4 | 3.3V |
| | 33 | JM3 | 34 | 3.3V |
| | 35 | JM3 | 20 | 3.3V |
| | 35 | JM2 | 22 | 3.3V |
| | 501 | JM2 | 38 | VMIO1 | MIO1 VREF is connected to resistor divider to support HSTL18 |
|
JTAG Interface
JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.
| Scroll Title |
|---|
| anchor | Table_SIP_JTG |
|---|
| title | JTAG pins connection |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
JTAG Signal | B2B Pin |
|---|
| TMS | JM2-12 | | TDI | JM2-10 | | TDO | JM2-8 | | TCK | JM2-6 |
|
PS7 UART
There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to PL pins.
...
| Scroll Title |
|---|
| anchor | Table_OBP |
|---|
| title | On board peripherals |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Chip/Interface | IC | PS7 Peripheral | Notes |
|---|
| SPI Flash | S25FL127SABMFV10 | QSPI0 | 16 MByte Flash | | I2C EEPROM | 24LC64 | I2C0 | 64 KByte EEPROM | | RTC I2C | RV-3029 | I2C0 |
| | RTC Interrupt | RV-3029 | GPIO - MIO0 |
| | User LED | LED Green | GPIO - MIO7 |
|
|
16 MByte Quad SPI Flash Memory
On-board QSPI flash memory S25FL127SABMFV10 is used to store initial FPGA configuration. Datasheet is provided in Texas Instruments. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
...