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Clock SourceSchematic NameFrequencyClock Input Destination
SiTime SiT8008BI oscillator, U10USB0_RCLK52.000000 MHzUSB 2.0 transceiver PHY U9, pin 26
SiTime SiT8008BI oscillator, U13ETH_CLK25.000000 MHzGigabit Ethernet PHY U12, pin 34
SiTime SiT8008BI oscillator, U7-25.000000 MHzQuad PLL clock generator U35, pin 3
DSC1123 oscillator, U23B505_CLK1150.0000 MHzPS GT Bank, dedicated for SATA interface

DSC1123 oscillator, U6

optional, not equipped

B505_CLK0100.0000 MHzPS GT Bank, dedicated for USB interface

Silicon Labs 570FBB000290DG, U45

optional, not equipped

B47_L5 (LVDS)250.MHzPL Bank clock capable input pins
SiTime SiT8008BI oscillator, U25CLK_CPLD2524.576000 MHzSystem Controller CPLD U35, pin 128

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 Date

Revision

ContributorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat

Page info
infoTypeModified by
dateFormatyyyy-MM-dd
typeFlat

  • correction typ U25 CLK

v.93John Hartfiel
  • update links

v.89Martin Rohrmüller
  • Typo

v.88
John Hartfiel
  • Typo correction Table 13
  • Typo correction Table 9
2017-11-15v.86Ali Naseri
  • DIP-switches section revised and updated

2017-11-13

v.82

Ali Naseri
  • updated B2B connector max. current rating
    per pin

2017-11-13

v.80

John Hartfiel
  • rework B2B section
2017-10-19

v.79

Ali Naseri
  • added additionally MGT lanes information

2017-10-18

v.75
Ali Naseri
  • added Power Rails section

2017-08-29

v.70



John Hartfiel
  • update document change history
  • published
2017-08-28v.69Ali Naseri
  • Initial document

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