Page History
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| MGT Bank | Type | Count of MGT Lanes | Schematic Names / Connector Pins | MGT Bank's Reference Clock Inputs from FMC Connector |
|---|---|---|---|---|
| 228 | GTH | 4 GTH lanes | B228_RX3_P, B228_RX3_N, pins J5-A10, J5-A11 B228_RX2_P, B228_RX2_N, pins J5-A6, J5-A7 B228_RX1_P, B228_RX1_N, pins J5-A2, J5-A3 B228_RX0_P, B228_RX0_N, pins J5-C6, J5-C7 | 1 reference clock signal (B228_CLK0) from FMC connector Si5345 CLK3 of prog. PLL on mounted SoM internally on-module |
| 229 | GTH | 4 GTH lanes | B229_RX3_P, B229_RX3_N, pins J5-B12, J5-B13 B229_RX2_P, B229_RX2_N, pins J5-B16, J5-B17 B229_RX1_P, B229_RX1_N, pins J5-A18, J5-A19 B229_RX0_P, B229_RX0_N, pins J5-A14, J5-A15 | 1 reference clock signal (B229_CLK0) from FMC connector Si5345 CLK2 of prog. PLL on mounted SoM internally on-module |
| 230 | GTH | 2 GTH lanes | B230_RX1_P, B230_RX1_N, pins J5-B4, J5-B5 B230_RX0_P, B230_RX0_N, pins J5-B8, J5-B9 | Si5345 CLK1 of prog. PLL on mounted SoM internally on-module |
Table 2: FMC connector pin-outs of available MGT-lanes of the MPSoC
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| Function | MGT Lane | Required Ref Clock | Clock Source | Comment | ||
|---|---|---|---|---|---|---|
| PCIe | PS 0 | 100 MHz | Si5345 ( CLK0 of prog. PLL on mounted SoM) | wired on carrier board - | ||
| USB3 | PS 1 | 100 MHz | Optional Oscillator U6 | Si5345 CLK4 of prog. PLL on mounted SoM | internally on-module wired, | |
| SATA | PS 2 | 150 MHz | Oscillator U23 | Si5345 CLK4 of prog. PLL on mounted SoM | internally on-module wired, | |
| DP.0 | PS 3 | 27 MHz | Si5345 CLK5 of prog. PLL on mounted SoM | DisplayPort GT SERDES Clock | - | module wired Si5345 CLK6 of prog. PLL on mounted SoM |
Table 6: PS GT Lane Assignment
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| Function | MGT Lane | Required Ref Clock | Clock Source | Comment | |
|---|---|---|---|---|---|
| FireFly | B128 MGT Lanes 0..3 | - | - | Si5345 CLK6 of prog. PLL on mounted SoM | internally on-module wired - |
| SFP | B230 MGT Lane 2 | 125 / 156.25 MHz | Si5345 ( CLK7 of prog. PLL on mounted SoM) | wired on carrier board - | |
| SFP | B230 MGT Lane 3 | 125 / 156.25 MHz | Si5345 ( CLK7 of prog. PLL on mounted SoM) | wired on carrier board - |
Table 6: MGT Lane Assignment
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Si5338 OTP can only be programmed two times, as different user configurations may required different setup, TEBF0808 is normally shipped with blank OTP.
For more information Si5338 at SiLabs.
| Note |
|---|
Refer to the TE0808 TRM for the internal wiring of the on-module 10-channel PLL clock generator with the clock input pins of the MGT banks. |
Oscillators
The TEBF0808 carrier board is equipped several on-board oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the on-board peripherals with reference clock-signals:
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The carrier board VCCO voltage 'FMC_VADJ' supplying the PL IO-banks of the SoM (bank 64, 65, 66, 48) is provided by DC-DC converter U8 and selectable by the pins 'FMC_VID0' ... 'FMC_VID2' of the System Controller CPLD U17.
| FMC_VID2 | FMC_VID1 | FMC_VID0 | FMC_VADJ Value |
|---|---|---|---|
| 0 | 1 | 0 | 1.8V |
| 0 | 1 | 1 | 1.5V |
| 1 | 0 | 0 | 1.25V |
| 1 | 0 | 1 | 1.2V |
Table 3: Bit patterns for fixed values of the FMC_VADJ voltage
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It is important that all PS and PL I/Os are tri-stated at power-on until the "Power Good"-signals are logically high, meaning that all on-module voltages have become stable and module is properly powered up.
Power Rails
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Voltages on B2B
Connectors
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Input/
Output
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-
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J2-154, J2-156, J2-158, J2-160,
J2-153, J2-155, J2-157, J2-159
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Internal voltage level
1.8V nominal output
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Internal voltage level
1.8V nominal output
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Internal voltage level
1.2V nominal output
Table 17: Power rails of the MPSoC module on accessible connectors
Bank Voltages
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Table 18: Range of MPSoC module's bank voltages
B2B connectors
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Overview
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