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Scroll Title |
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anchor | Table_SIP_B2B |
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title | General PL I/O to B2B connectors information |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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FPGA Bank | Type | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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13 | HR | J1 | 48 Single | -end ended (24 Diff) | VCCO_13 | variable from carrier | 500 | MIO | J1 | 4 | Single endSingel ended | 3.3V |
| 501 | MIO | J2 | 38 | Single endSingel ended | VMIO1 | variable from carrier | 33 | HR | J3 | 34 Single | end ended (17 Diff) | 3.3V |
| 35 | HR | J3 J2 | 20 Single | end end
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Ethernet PHY
Ethernet pins connections to Board to Board (B2B). Ethernet components ETH1 and ETH2 are connected to B2B connector J3.
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