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Name | Direction | Pin | Description | ||||
---|---|---|---|---|---|---|---|
ACBUS4 | in | 96 | FTDI / currently_not_used | ||||
ACBUS5 | in | 88 | FTDI / currently_not_used | ||||
ADBUS4 | out | 98 | FTDI / get M_TCK | ||||
ADBUS7 | out | 97 | FTDI / currently_not_used | ||||
BDBUS0 | inout | 87 | FTDI / Module UART0.RX << FTDI | ||||
BDBUS1 | inout | 86 | FTDI /Module UART0.TX >> FTDI | ||||
C_TCK | out | 81 | JTAG Module | ||||
C_TDI | out | 84 | JTAG Module | ||||
C_TDO | in | 83 | JTAG Module | ||||
C_TMS | out | 85 | JTAG Module | ||||
CM0 | in | 67 | DIP Switch S3-M1 | ||||
CM1 | in | 66 | DIP Switch S3-M2 | ||||
CM2 | in | 51 | DIP Switch S4-4, only on REV6+ | ||||
EN_FMC | out | 35 | VADJ Power on | ||||
EN1 | out | 53 | Power Enable Pin for Module CPLD | ||||
JTAGEN | -- | 82 | Enable JTAG access to carrier CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access) Set DIP Switch S3-JTAGEN to ON, for module access. | ||||
JTAGMODE | out | 58 | Enable JTAG access to module CPLD for Firmware update (zero: JTAG routed to module FPGA, one: Module CPLD access) | ||||
M_TCK | in | 91 | JTAG FTDI | ||||
M_TDI | in | 94 | JTAG FTDI | ||||
M_TDO | out | 95 | JTAG FTDI | ||||
M_TMS | in | 90 | JTAG FTDI | ||||
MIO10 | inout | 32 | MIO / used by RGPIO Bus | ||||
MIO11 | inout | 31 | MIO / used by RGPIO Bus | ||||
MIO12 | inout | 39 | MIO / used by RGPIO Bus | ||||
MIO13 | inout | 34 | MIO / used by RGPIO Bus | ||||
MIO14 | inout | 40 | MIO / Module UART0.RX << BDBUS0 | ||||
MIO15 | inout | 30 | MIO / Module UART0.TX >> BDBUS1 | ||||
MODE | out | 28 | Boot Mode for Zynq Devices (Flash or SD) | ||||
NOSEQ | inout | 29 | / currently_not_used | ||||
PGOOD | inout | 27 | / currently_not_used | ||||
PHY_LED1 | out | 45 | LED Ethernet | ||||
PHY_LED1_A | out | 49 | LED Ethernet / currently_not_used | ||||
PHY_LED2 | out | 47 | LED Ethernet | ||||
PHY_LED2_A | out | 48 | LED Ethernet / currently_not_used | ||||
POK_FMC | in | 36 | FMC VADJ Power Good | ||||
RESIN | out | 54 | Module Reset | REVISION_DETECION | in | 57 | only on REV6+, is set to GND |
S1 | in | 75 | User Button / used by RGPIO Bus | ||||
S2 | in | 74 | User Button / Global Reset | ||||
SD_DETECT | in | 42 | SD Detection / used for FPGA Boot Mode | ||||
SD_WP | in | 43 | SD / RGPIO Bus | ||||
ULED1 | out | 78 | LED D6 | ||||
ULED2 | out | 77 | LED D7 | ||||
ULED3 | out | 76 | LED D8 | ||||
ULED4 | out | 65 | LED D9 | ||||
ULED5 | out | 71 | LED D4 | ||||
ULED6 | out | 70 | LED D15 | ||||
ULED7 | out | 69 | LED D14 | ||||
ULED8 | out | 68 | LED D5 | ||||
USB_OC | in | 99 | USB Over Current | ||||
USR0 | in | 64 | DIP Switch S4-1 / used by RGPIO Bus (PCB REV04 only) | ||||
USR1 | in | 61 | DIP Switch S4-2 / used by RGPIO Bus (PCB REV04 only) | ||||
USR2 | in | 60 | DIP Switch S4-3 / used by RGPIO Bus (PCB REV04 only) | ||||
USR3 | in | 59 | DIP Switch S4-4 / used by RGPIO Bus (PCB REV04 only) | ||||
VID0 | out | 37 | VADJ Voltage selection (EN5335QI) | ||||
VID1 | out | 38 | VADJ Voltage selection (EN5335QI) | ||||
VID2 | out | 41 | VADJ Voltage selection (EN5335QI) | ||||
X6 | in | 19 | RGPIO Bus | ||||
Y0 | 15 | / currently_not_used | |||||
Y1 | 14 | / currently_not_used | |||||
Y2 | in | 13 | RGPIO CLK | ||||
Y3 | out | 10 | RGPIO TX | ||||
Y4 | in | 9 | RGPIO RX | ||||
Y5 | 8 | / currently_not_used | |||||
Y6 | in | 7 | RGPIO Bus |
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