Table of contents
CPLD Device with designator U14: LCMX02-1200HC
- Power Management
- Reset Management
- Boot Mode Controller
- FPGA UART routing
- RGPIO Interface to FPGA
Firmware Revision and supported PCB Revision
|Name / opt. VHD Name||Direction||Pin||Description|
|ACBUS4||in||96||FTDI / currently_not_used|
|ACBUS5||in||88||FTDI / currently_not_used|
|ADBUS4||out||98||FTDI / get M_TCK|
|ADBUS7||out||97||FTDI / currently_not_used|
|BDBUS0||inout||87||FTDI / Module UART0.RX << FTDI|
|BDBUS1||inout||86||FTDI /Module UART0.TX >> FTDI|
|CM0||in||67||DIP Switch S3-M1|
|CM1||in||66||DIP Switch S3-M2|
|EN_FMC||out||35||VADJ Power on|
|EN1||out||53||Power Enable Pin for Module CPLD|
|JTAGEN||--||82||Enable JTAG access to carrier CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access)|
Set DIP Switch S3-JTAGEN to ON, for module access.
|JTAGMODE||out||58||Enable JTAG access to module CPLD for Firmware update (zero: JTAG routed to module FPGA, one: Module CPLD access)|
|MIO10||inout||32||MIO / used by RGPIO Bus|
|MIO11||inout||31||MIO / used by RGPIO Bus|
|MIO12||inout||39||MIO / used by RGPIO Bus|
|MIO13||inout||34||MIO / used by RGPIO Bus|
|MIO14||inout||40||MIO / Module UART0.RX << BDBUS0|
|MIO15||inout||30||MIO / Module UART0.TX >> BDBUS1|
|MODE||out||28||Boot Mode for Zynq Devices (Flash or SD)|
|PHY_LED1_A||out||49||LED Ethernet / currently_not_used|
|PHY_LED2_A||out||48||LED Ethernet / currently_not_used|
|POK_FMC||in||36||FMC VADJ Power Good|
|S1||in||75||User Button / used by RGPIO Bus|
|S2||in||74||User Button / Global Reset|
|SD_DETECT||in||42||SD Detection / used for FPGA Boot Mode|
|SD_WP||in||43||SD / RGPIO Bus|
|USB_OC||in||99||USB Over Current|
|USR0||in||64||DIP Switch S4-1 / used by RGPIO Bus (PCB REV04 only)|
|USR1||in||61||DIP Switch S4-2 / used by RGPIO Bus (PCB REV04 only)|
|USR2||in||60||DIP Switch S4-3 / used by RGPIO Bus (PCB REV04 only)|
|USR3||in||59||DIP Switch S4-4 / used by RGPIO Bus (PCB REV04 only)|
|VID0||out||37||VADJ Voltage selection (EN5335QI)|
|VID1||out||38||VADJ Voltage selection (EN5335QI)|
|VID2||out||41||VADJ Voltage selection (EN5335QI)|
JTAGEN set carrier board CPLD into the chain for firmware update. In normal mode JTAG is routed directly to Module. Set S3-ENJTAG to OFF to get access to carrier CPLD.
JTAGMODE set module CPLD into the chain for firmware update. In normal mode JTAG is routed directly to FPGA. Set S3-ENJTAG, S3-M1 and S3-M2 to ON to get access to module CPLD. Attention VADJ is set to 1.8V in this mode.
EN1 is set to logical one after delay.
EN_FMC is set to logical one after delay.
VADJ Selection Table:
|ON||ON||VADJ: 1.8V, Attention: Also Module CPLD JTAG access is enabled, see JTAG description.|
RESIN (negative Reset) to module, can be set by S2 button.
Boot mode is set to SD-Boot, when SD-Card is detected.
RGPIO Master is a 32Bit Remote GPIO Interface to talk with FPGA over 3 lanes.
|RGPIO Pin to FPGA||Value|
|RGPIO Pin from FPGA||Value|
|ULED1||not external reset / RGPIO(0), when FPGA Interface is detected|
|ULED2||(M1=off,M2=off) / RGPIO(1), when FPGA Interface is detected|
|ULED3||Module UART0.RX / RGPIO(2), when FPGA Interface is detected|
|ULED4||Module UART0.TX / RGPIO(3), when FPGA Interface is detected|
|ULED5||SD_DETECT / RGPIO(4), when FPGA Interface is detected|
|ULED6||(M1=on,M2=off) / RGPIO(5), when FPGA Interface is detected|
|ULED7||X6 / RGPIO(6), when FPGA Interface is detected|
|ULED8||Y6 / RGPIO(7), when FPGA Interface is detected|
Appx. A: Change History
REV01 to REV02
- Power Management
- VADJ is switchable by S3 dip switches
- Reset Management
- only little changes
- RGPIO Interface to FPGA
- RGPIO support
- new Order and accessible by RGPIO
- Module CPLD access is possible know
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
|Date||Document Revision||CPLD Firmware Revision||Supported PCB Revision||Authors||Description|
|REV02||REV03, REV04||document style update|
|REV02||REV03, REV04||Revision 02 finished|
Appx. B: Legal Notices
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