Overview

CPLD Device with designator U14: LCMX02-1200HC

Feature Summary

  • Power Management
  • Reset Management
  • Boot Mode Controller
  • FPGA UART routing
  • I2C to GPIO

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinPull up/ downBank PowerDescription
ACBUS4          in96UP3.3VFTDI / It can be read via i2c to GPIO. ( GPIO_input(22) )
ACBUS5          in88UP3.3VFTDI /  It can be read via i2c to GPIO. ( GPIO_input(23) )
ADBUS4          out98NONE3.3VFTDI  / M_TCK is connected to ADBUS4.
ADBUS7          out97UP3.3VFTDI / currently_not_used
BDBUS0          inout87NONE3.3VFTDI / Module UART0-RX << FTDI
BDBUS1          inout86NONE3.3VFTDI  /Module UART0-TX >> FTDI
C_TCKout81DOWN3.3VTCK  JTAG port pin connected to Module
C_TDIout84DOWN3.3VTDI  JTAG  port pin connected to Module
C_TDOin83DOWN3.3VTDO JTAG port pin connected to Module
C_TMSout85UP3.3VTMS JTAG port pin connected to Module
CM0in67UP3.3VDIP Switch S3-M1 / Used to select FMC_VADJ voltage
CM1in66UP3.3VDIP Switch S3-M2 / Used to select FMC_VADJ voltage 
EN_FMC          out35NONE3.3VPower SoC (EN5335QI) power on signal (VADJ enable)
 EN1             out53UP3.3VPower Enable Pin for CPLD of module
JTAGEN--82UP3.3VEnable JTAG access to carrier CPLD for Firmware update ( Zero: JTAG routed to module, One: CPLD access ) Set DIP Switch S3-JTAGEN (S3-C)  to ON, for module access.
JTAGMODEout58NONE3.3VEnable JTAG access to module CPLD for firmware programming. If JTAGMODE = '0' JTAG port is routed to FPGA of module otherwise JTAG port is routed to CPLD of module.
M_TCK           in91UP3.3VTCK   JTAG port pin connected to  FTDI chip
M_TDI           in94UP3.3VTDI   JTAG port pin connected to  FTDI chip
M_TDO           out95UP3.3VTDO  JTAG port pin connected to  FTDI chip
M_TMS           in90UP3.3VTMS  JTAG port pin connected to  FTDI chip
MIO10           inout32UP3.3VMIO / I2C SCL pin of CPLD of TE0705
MIO11           inout31UP3.3VMIO / I2C SDA pin of CPLD of TE0705
MIO12           inout39NONE3.3V MIO
MIO13           inout34NONE3.3V MIO
MIO14           inout40NONE3.3VMIO / Module UART0-RX << BDBUS0
MIO15           inout30NONE3.3VMIO / Module  UART0-TX >> BDBUS1
MODE            out28DOWN3.3VBoot mode select pin for Zynq Devices
NOSEQ           inout29UP3.3VFor TE0715 module is connected to M_TMS JTAG pin for programming the CPLD of TE0715. For other modules this pin is used as GPIO.
PGOOD           inout27UP3.3VFor TE0715 module is connected to M-TDO JTAG pin for programming the CPLD of TE0715. For other modules this pin is used as either GPIO pin or boot mode selection pin.
PHY_LED1        out45NONE3.3VRJ45 connector right LED Green LED anode and yellow LED cathode / State of this pin indicates PGOOD and NOSEQ signal state.
PHY_LED1_A      out49NONE3.3VRJ45 connector right LED Green LED cathode and yellow LED anode / State of this pin indicates PGOOD and NOSEQ signal state.
PHY_LED2        out47NONE3.3VRJ45 connector left LED Green LED cathode and yellow LED anode / State of this pin indicates EN_FMC ( Power Ok of EN5335QI PowerSoC)
PHY_LED2_A      out48NONE3.3VRJ45 connector left LED Green LED anode and yellow LED cathode / State of this pin indicates EN_FMC ( Power Ok of EN5335QI PowerSoC)
POK_FMC         in36UP3.3VFMC VADJ Power Good 
RESIN           out54UP3.3VModule reset that connected to S2 push button
S1              in75UP3.3VUser button
S2              in74UP3.3VUser button / Global Reset push button
SD_DETECT       in42UP3.3VSD card detection / Used for FPGA Boot Mode selection. Connected to MODE pin ,if USR0 = OFF  for PCB REV04.
SD_WP           in43UP3.3VSD write protect
ULED1           out78NONE3.3V

LED D6  / Connected to MODE0 signal . If MODE0='1' → FMC_VADJ = 1.8V
Connected to GPIO_output(0) , if S1 push button is pushed.

ULED2           out77NONE3.3V

LED D7  / Connected to MODE1 signal. If MODE1='1' → FMC_VADJ = 2.5V
Connected to GPIO_output(1) , if S1 push button is pushed.

ULED3           out76NONE3.3VLED D8  / Connected to MODE2 signal. If MODE2='1' → FMC_VADJ = 3.3V
Connected to GPIO_output(2) , if S1 push button is pushed.
ULED4           out65NONE3.3VLED D9  / Connected to MODE3 signal. If MODE3='1' → FMC_VADJ = 1.8V
Connected to GPIO_output(3) , if S1 push button is pushed.
ULED5           out71NONE3.3VLED D4  / Connected to RESET push button (S2)
Connected to GPIO_output(4) , if S1 push button is pushed.
ULED6           out70NONE3.3V

LED D15 / Connected to SD_DETECT. f LED is ON --> MODE = '1' (QSPI boot mode) else MODE = '0' (SD card boot mode)
Connected to GPIO_output(5) , if S1 push button is pushed.

ULED7           out69NONE3.3VLED D14 / Connected to UART0-TX
Connected to GPIO_output(6) , if S1 push button is pushed.
ULED8           out68NONE3.3VLED D5   / Connected to UART0-RX
Connected to GPIO_output(7) , if S1 push button is pushed.
USB_OC          in99UP3.3VUSB Over Current
USR0*in64NONE3.3VDIP Switch S4-1 / Used to determine if TE0715 CPLD access is activated. If USR0 = ON → Access to TE0715 CPLD , If USR0 = OFF  → No access to TE0715 CPLD
USR1*in61NONE3.3VDIP Switch S4-2 / USR1 can set or reset NOSEQ, if USR0 = OFF
USR2*in60NONE3.3VDIP Switch S4-3 / USR2 can set set or reset PGOOD, if USR0 = OFF
USR3*in59NONE3.3V

DIP Switch S4-4 / Connected to JTAGMODE signal for accessing to CPLD of module.
USR3 = ON → No access to CPLD of module , USR3 = OFF → Access to CPLD of module

VID0            out37NONE3.3VVADJ Voltage selection of power SoC (EN5335QI)
VID1            out38NONE3.3VVADJ Voltage selection of power SoC (EN5335QI)
VID2            out41NONE3.3VVADJ Voltage selection of power SoC (EN5335QI)
X6              in19NONE3.3VConnection pin between CPLD of carrier board and FPGA on the module via B2B connector. It can be read via i2c to GPIO.( GPIO_input(31) )
Y0              in15DOWN3.3VConnection pin between CPLD of carrier board and FPGA on the module via B2B connector. It can be read via i2c to GPIO.( GPIO_input(24) )
Y1              in14DOWN3.3VConnection pin between CPLD of carrier board and FPGA on the module via B2B connector. It can be read via i2c to GPIO.( GPIO_input(25) )
Y2              in13DOWN3.3VConnection pin between CPLD of carrier board and FPGA on the module via B2B connector. It can be read via i2c to GPIO.( GPIO_input(26) )
Y3              in10DOWN3.3VConnection pin between CPLD of carrier board and FPGA on the module via B2B connector. It can be read via i2c to GPIO.( GPIO_input(27) )
Y4              in9NONE3.3VConnection pin between CPLD of carrier board and FPGA on the module via B2B connector. It can be read via i2c to GPIO.( GPIO_input(28) )
Y5              in8NONE3.3VConnection pin between CPLD of carrier board and FPGA on the module via B2B connector. It can be read via i2c to GPIO.( GPIO_input(29) )
Y6              in7NONE3.3VConnection pin between CPLD of carrier board and FPGA on the module via B2B connector. It can be read via i2c to GPIO.( GPIO_input(30) )

*Note: USR dip switch (S4-Dip Switch) does not exist in PCB revision 3 or older.

Functional Description

User Dip Switch

User has 8 dip switches and two push buttons in total on the board. In the following tables you can find more information about it.

DIP Switch S3
S3-1S3-2S3-3S3-4Description
CM1**CM0**JTAGEN**MIO0*JTAGEN set carrier board CPLD into the chain for firmware update.

*Note: MIO0 is not connected to CPLD chip.
**Pin names in the schematic of board. Names on the board (labels) : CM1 → M2 , CM0 → M1, JTAGEN → ENJTAG


DIP Switch S4*
S4-1S4-2S4-3S4-4Description
USR0USR1USR2USR3

*Note: This dip switch exists only for PCB revision 4 or later.


USR0Description
OFFNo access to TE0715 CPLD
ONAccess to TE0715 CPLD
USR1Description
OFFNOSEQ = '0' if USR0 = OFF else NOSEQ = M_TMS
ONNOSEQ = '1' if USR0 = OFF else NOSEQ = M_TMS
USR2Description
OFFPGOOD = '0' if USR0 = OFF else PGOOD = 'Z'
ONPGOOD = '1' if USR0 = OFF else PGOOD = 'Z'
USR3Description
OFFJTAGMODE = '0' →  JTAG routed to module FPGA
ONJTAGMODE = '1'  → Access to CPLD of module

JTAG

In normal mode JTAG is routed directly to the module. JTAGEN set carrier board CPLD into the chain for firmware update. Set S3-3 (ENJTAG) to OFF to get access to carrier CPLD. JTAGMODE set module CPLD into the chain for firmware update. In normal mode  JTAG is routed directly to FPGA. To access CPLD of TE0715 JTAG port must be routed to special pins same as NOSEQ pin. Therefore in PCB REV04 or later USR0 is used to access CPLD of TE0715 module. For PCB REV03  CM0(S3-2) and CM1(S3-1) dip switches will be used for this purpose. In this case user must be careful because these dip switches are used to select FMC_VADJ output voltage too. 

Warning

For some 4x5 modules if FMC_VADJ voltage is set incorrectly, the FPGA can be damaged !

More information about JTAG pins can be found in the following table:

PinConnected toCondition for PCB REV04 or laterCondition for PCB REV03*DescriptionConnected toCondition for PCB REV04 or laterCondition for PCB REV03*Description
M_TMSNOSEQUSR0 = ONCM1(S3-1)=ON and CM0(S3-2)=ONAccess to TE0715 CPLDC_TMSUSR0 = OFFCM1(S3-1)=OFF or CM0(S3-2)=OFFNo access to TE0715 CPLD. In this case NOSEQ can be used as user IO.
M_TCKMODEUSR0 = ONCM1(S3-1)=ON and CM0(S3-2)=ONAccess to TE0715 CPLDC_TCKUSR0 = OFFCM1(S3-1)=OFF or CM0(S3-2)=OFFNo access to TE0715 CPLD. In this case MODE will be used as SD card detection.
M_TDIEN1USR0 = ONCM1(S3-1)=ON and CM0(S3-2)=ONAccess to TE0715 CPLDC_TDIUSR0 = OFFCM1(S3-1)=OFF or CM0(S3-2)=OFFNo access to TE0715 CPLD. In this case EN1 is '1'.
C_TDOPGOODUSR0 = ONCM1(S3-1)=ON and CM0(S3-2)=ONAccess to TE0715 CPLDM_TDOUSR0 = OFFCM1(S3-1)=OFF or CM0(S3-2)=OFFNo access to TE0715 CPLD. In this case PGOOD can be used as user IO.

*Note: This case is valid if jed file for accessing to TE0715 CPLD is programmed on the TE0705 carrier board CPLD.


PinCPLD PinConnected toDescription
JTAGEN82S3-3 Dip Switch (ENJTAG)To access CPLD of carrier board, JTAGEN must be set to '1'. ( ENJTAG (S3-3) = OFF  )
JTAGMODE58B2B JB1-90

To access CPLD of module this pin must be set to high.

PCB REV04 (Default)
StatusS4-1(USR0)S4-4(USR3)S3-3(ENJTAG)Description
Access to carrier board CPLD--------OFF
Access to FPGA of moduleOFFOFFON
Access to CPLD of moduleOFFONON
Access to the TE0715 CPLDONONON
JTAGMODEConditionDescription
0USR3 = OFFTo access FPGA of module
1USR3 = ONTo access CPLD of module
PCB REV03 (Optional)
StatusCM1(S3-1)CM0(S3-2)S3-3(ENJTAG)FMC_VADJDescription
Access to carrier board CPLD--------OFF----
Access to FPGA of moduleOFFOFFON1.8V
Access to FPGA of moduleOFFONON3.3V
Access to FPGA of moduleONOFFON2.5V

Access to CPLD of module*

ONONON1.8V

Attention: It is exists two separate jed file to access the CPLD on the TE0715 module and other modules.

*For accessing to CPLD of TE0715 , special jed file in optional folder must be programmed on the CPLD of carrier board TE0705. If jed file for accessing to CPLD of TE0715 (Access to TE0715 CPLD) is programmed on the CPLD of carrier board, CPLD of other modules can not be programmed more. In this case , if user need to update firmware CPLD of the module, user should program other jed file (No Access to TE0715 CPLD) on the carrier board CPLD.

JTAGMODEConditionDescription
0CM1(S3-1)= OFF or CM0(S3-2)= OFFTo access FPGA of module
1CM1(S3-1)= ON and CM0(S3-2)= ONTo access CPLD of module

Power

To adjust output voltage of EN5335QI power SoC (FMC_VADJ ) CM1(S3-1)and CM0(S3-2) are used. EN_FMC pin is for activating this power SoC. EN_FMC signal will be set to '1' to enable the power SoC after power on. VID0, VID1 and VID2 are connected to EN5335QI PowerSoC chip to select output voltage.

EN5335QI Power SoC  Voltage Select Lines
VID2VID1VID0VoutDescription
0003.3V
0012.5V
0101.8V
0111.5VNot selectable
1001.25VNot selectable
1011.2VNot selectable
1100.8VNot selectable
111Reserved---
EN5335QI Power SoC output voltageCM1(S3-1)CM0(S3-2)Description
1.8VOFFOFFAccess to FPGA of module for PCB REV03
3.3VOFFONAccess to FPGA of module for PCB REV03
2.5VONOFFAccess to FPGA of module for PCB REV03
1.8VONONAccess to TE0715 CPLD or CPLD of other modules for PCB REV03*

*There are for PCB REV03 two jed files in optional folder. One of them is for accessing to TE0715 CPLD and other jed file is for accessing to other 4x5 modules except TE0715. For PCB REV03 both CPLD of TE0715 and other modules except TE0715 can not be accessed via one jed file for CPLD of carrier board.

Reset

RESIN pin (active low) of module can be set by S2 button.

PinCPLD PinConnected toDescription
RESIN54S2 push button / B2B JB2-17Active-low

Boot mode

When SD card is plugged , SD_DETECT signal will be set to '0'. If CM0(S3-2) and CM1(S3-1) for PCB REV03 and USR0 for PCB REV04 are not set for accessing to CPLD of TE0715 module, SD_DETECT will be connected to MODE pin. MODE pin is responsible to set boot mode. If MODE pin is set to high, QSPI boot mode is selected else SD card boot mode is chosen. 

PinCPLD PinIn hardware connected toConnected to (Firmware of PCB REV04)Connected to (Firmware of PCB REV03)Description
SD_DETECT42SD card detection pinMODE pin if  USR0 = OFFMODE pin if CM1(S3-1)= OFF or CM0(S3-2)= OFF


PCB REV04 (Default)
Boot Mode*S4-3 (USR2)SD CardDescription
JTAG ModeOFFPluggedPGOOD = '0' , MODE = '0'
eMMC ModeOFFRemovedPGOOD = '0' , MODE = '1'
SD Card Boot ModeONPluggedPGOOD = '1' , MODE = '0'
QSPI Boot ModeONRemovedPGOOD = '1' , MODE = '1'

 *It is valid only for SoC. Note that after any change in dip switches carrier board must be reset , to change boot mode correctly.

PCB REV03 (Optional)

The following boot mode table is not valid while CM1 = ON and  CM0 = ON and jed file for accessing to TE0715 CPLD is programmed on the CPLD of carrier board for all 4x5 modules.

Boot Mode*vir_usr2**SD CardRelated Command in linux***Related Command in FSBL***Description
JTAG Mode1Plugged
i2cset -y 0 0x30 0x02 0x01
iic_write(0x30,0x02,0x01)
PGOOD = '0' , MODE = '0'
eMMC Mode1Removed
i2cset -y 0 0x30 0x02 0x01
iic_write(0x30,0x02,0x01)
PGOOD = '0' , MODE = '1'
SD Card Boot Mode0Plugged
i2cset -y 0 0x30 0x02 0x00
iic_write(0x30,0x02,0x00)
PGOOD = '1' , MODE = '0'
QSPI Boot Mode0Removed
i2cset -y 0 0x30 0x02 0x00
iic_write(0x30,0x02,0x00)
PGOOD = '1' , MODE = '1'

 *It is valid only for SoC. Note that after any change in vir_usr2 oder SD Card detection switch carrier board must be reset , to change boot mode correctly.
**vir_usr2 can be changed only via I2C to GPIO in linux console or in FSBL code. Its default value is '0'. If no I2C to GPIO is designed in Vivado and Linux, vir_usr2 can not be changed. Because of its default value after power on ('0') user can choose only SD card boot mode and QSPI boot mode by plugging and removing the SD card respectively.  
***After setting vir_usr2 via I2C to GPIO it is necessary to reset the board manually to change boot mode.

I2C to GPIO

I2C to GPIO is a subsystem in firmware of CPLD that provides an i2c interface that writes received data to GPIO_output 8 bit registers or reads  8 bit GPIO_input registers and send read data to i2c bus. 

I2C bus is connected to MIO10 ( SCL signal) and MIO11 (SDA signal). MIO10 to MIO15 are direct connection between CPLD of TE0705 and FPGA on the module through B2B connector. If in FPGA design exists  no i2c interface for MIO10 and MIO11, this block will be unused. More information about MIO10 to MIO15 are shown in the following table for whole Trenz Electronic 4x5 modules and TE0705 carrier board:

B2B PinB2B JB1-96B2B JB1-94B2B JB1-100B2B JB1-98B2B JB1-91B2B JB1-86
Carrier boardLabel / Firmware functionLabel / Firmware functionLabel / Firmware functionLabel / Firmware functionLabel / Firmware functionLabel / Firmware functionDescription
TE0705MIO10 / I2C-SCLMIO11 / I2C-SDAMIO12 / GPIOMIO13 / GPIOMIO14 / UART0-RXMIO15 / USRT0-TXMIO10 and MIO11 are used in CPLD firmware as I2C SCL and SDA  respectively.
B2B PinB2B JM1-95B2B JM1-93B2B JM1-99B2B JM1-97B2B JM1-92B2B JM1-85
Module Label / Chip pinLabel / Chip pinLabel / Chip pinLabel / Chip pinLabel / Chip pinLabel / Chip pinDescription
TEM0007I2C_CON_SCL / A3I2C_CON_SDA / E3UART_CON_TX / C2USRT_CON_RX / D3UART_RX / H2UART_TX / H5MIO10 and MIO11 are already set in test_design of TEM0007 as SCL and SDA respectively.
TE0710B14_IO2 / R10B14_IO6 / L18B14_IO7 / T11B14_IO3 / M18B16_IO4 / A8B16_IO0 / B8By using an external IIC IP core B14_IO2 and B14_IO6 can be used as I2C SCL and SDA respectively.
TE0711B14_IO2 / M13B14_IO6 / L18B14_IO7 / R16B14_IO3 / M18B14_IO4 / N17B14_IO0 / R10By using an external IIC IP core B14_IO2 and B14_IO6 can be used as I2C SCL and SDA respectively. 
TE0712B14_L4_P / T21B14_L9_N / Y22B14_L24_N / R17B14_L4_N / U21B14_L24_P / P16B14_L18_N / U18By using an external IIC IP core B14_L4_P and B14_L9_N can be used as I2C SCL and SDA respectively. 
TE0713B14_L4_P / T21B14_L9_N / Y22B14_L24_N / R19B14_L4_N / U21B14_L24_P / P19B14_L18_N / U18By using an external IIC IP core B14_L4_P and B14_L9_N can be used as I2C SCL and SDA respectively. 
TE0741MIO10 / B14_L22MIO11 / B14_K21MIO12 / B14_H23MIO13 / B14_K22MIO14 / B14_J21MIO15 / B14_G24By using an external IIC IP core B14_L22 and B14_K21 can be used as I2C SCL and SDA respectively. 
TE0841B65_SCL / Y19B65_SDA / AA19B65_L3_N / AF23B65_L3_P / AF22B65_L2_N / AH24B65_L4_N / AG24By using an external IIC IP core B65_SCL and B65_SDA  can be used as I2C SCL and SDA respectively. 
TE0715MIO10 / G16MIO11 / B19MIO12 / C18MIO13 / A17MIO14 / B17MIO15 / E17MIO10 and MIO11 can be set as SCL and SDA for I2C0 of  TE0715 respectively.
TE0720MIO10 / G7MIO11 / B4MIO12 / C5MIO13 / A6MIO14 / B6MIO15 / E6MIO10 and MIO11 are already set as as SCL and SDA for I2C0 in test_design of TE0720 respectively.
TE0820MIO26 / L15MIO27 / J15MIO28 / K15MIO29 / G16MIO30 / F16MIO31 / H16MIO26 and MIO27 can be set only for I2C0 of  FPGA and this bus is already used for another components same as EEPROM and PLL chip. If MIO10 and MIO11 are used as I2C bus for data communication with CPLD, then there are no access to PLL and EEPROM chip.
TE0821MIO26 / L15MIO27 / J15MIO28 / K15MIO29 / G16MIO30 / F16MIO31 / H16MIO26 and MIO27 can be set only for I2C0 of  FPGA and this bus is already used for another components same as EEPROM and PLL chip. If MIO10 and MIO11 are used as I2C bus for data communication with CPLD, then there are no access to PLL and EEPROM chip. 
TE0823MIO26 / L15MIO27 / J15MIO28 / K15MIO29 / G16MIO30 / F16MIO31 / H16MIO26 and MIO27 can be set only for I2C0 of  FPGA and this bus is already used for another components same as EEPROM and PLL chip. If MIO10 and MIO11 are used as I2C bus for data communication with CPLD, then there are no access to PLL and EEPROM chip. 

There are more additional connections between CPLD and FPGA on the module , that are listed in the following table:

CPLD PinCarrier board B2B PinModule B2B PinIn firmware used asDescription
X6B2B JB1-84B2B JM1-83No specific function. It can only be read by GPIO_input. It can be read via i2c to GPIO.  ( GPIO_input(31) )
Y0B2B JB2-76B2B JM2-75No specific function. It can only be read by GPIO_input.It can be read via i2c to GPIO.  ( GPIO_input(24) )
Y1B2B JB2-78B2B JM2-77No specific function. It can only be read by GPIO_input. It can be read via i2c to GPIO.  ( GPIO_input(25) )
Y2B2B JB2-82B2B JM2-81No specific function. It can only be read by GPIO_input. It can be read via i2c to GPIO.  ( GPIO_input(26) )
Y3B2B JB2-84B2B JM2-83No specific function. It can only be read by GPIO_input. It can be read via i2c to GPIO.  ( GPIO_input(27) )
Y4B2B JB2-86B2B JM2-85No specific function. It can only be read by GPIO_input. It can be read via i2c to GPIO.  ( GPIO_input(28) )
Y5B2B JB2-88B2B JM2-87No specific function. It can only be read by GPIO_input. It can be read via i2c to GPIO.  ( GPIO_input(29) )
Y6B2B JB2-90B2B JM2-89No specific function. It can only be read by GPIO_input. It can be read via i2c to GPIO.  ( GPIO_input(30) )

It is depends on the module , which bank and pin of FPGA is connected to the module B2B pins that are written in this table.

UART

PinCPLD PinConnected toModule UART SignalDescription
MIO1440B2B JB1-91UART0-RXIn firmware MIO14  <= BDBUS0
MIO1530B2B JB1-86UART0-TXIn firmware BDBUS1 <= MIO15

NOSEQ

NOSEQ is used as TMS signal of JTAG port to program CPLD of TE0715 module. NOSEQ can be used as GPIO pin by user too. It can be controlled differentially for PCB REV03 and REV04 as in the following table is shown:

NOSEQCondition for PCB REV04 or laterCondition for PCB REV03Related command in linuxDescription
'0'USR1 = OFF and USR0 = OFF

GPIO_output [15:8] = 0x01 , if access to TE0715 is programmed on the carrier board CPLD and CM1(S3-1)= OFF or CM0(S3-2)= OFF

GPIO_output [15:8] = 0x01 , if no access to TE0715 CPLD is programmed on the carrier board CPLD , it is not dependent on CM0(S3-2) and CM1(S3-1).

i2cset -y 0 0x30 0x01 0x01
If module has no i2c interface for MIO10 and MIO11 pins in vivado and linux design , this option for PCB REV03 does not work.
'1'USR1 = ON and USR0 = OFF

GPIO_output [15:8] = 0x00 , if access to TE0715 is programmed on the carrier board CPLD and CM1(S3-1)= OFF or CM0(S3-2)= OFF

GPIO_output [15:8] = 0x00 , if no access to TE0715 CPLD is programmed on the carrier board CPLD, it is not dependent on CM0(S3-2) and CM1(S3-1).

i2cset -y 0 0x30 0x01 0x00 
If module has no i2c interface for MIO10 and MIO11 pins in vivado and linux design , this option for PCB REV03 does not work.

PGOOD

PGOOD pin is used as TDO JTAG signal to program CPLD of TE0715 module. PGOOD pin is used to select boot mode for SoC modules too. After booting user can use PGOOD as GPIO pin. PGOOD can be set or reset differentially for PCB REV04 and REV03 as shown:

PGOODCondition for PCB REV04 or laterCondition for PCB REV03Related command in linuxDescription
'0'USR2 = OFF and USR0 = OFF

GPIO_output [23:16] = 0x01 , if access to TE0715 is programmed on the carrier board CPLD and CM1(S3-1)= OFF or CM0(S3-2)= OFF

GPIO_output [23:16] = 0x01 , if no access to TE0715 CPLD is programmed on the carrier board CPLD, it is not dependent on CM0(S3-2) and CM1(S3-1).

i2cset -y 0 0x30 0x02 0x01
If module has no i2c interface for MIO10 and MIO11 pins in vivado and linux design , this option for PCB REV03 does not work.
'1'USR2 = ON and  USR0 = OFF

GPIO_output [23:16] = 0x00 , if access to TE0715 is programmed on the carrier board CPLD and CM1(S3-1)= OFF or CM0(S3-2)= OFF

GPIO_output [23:16] = 0x00 , if no access to TE0715 CPLD is programmed on the carrier board CPLD, it is not dependent on CM0(S3-2) and CM1(S3-1).

i2cset -y 0 0x30 0x02 0x00
If module has no i2c interface for MIO10 and MIO11 pins in vivado and linux design , this option for PCB REV03 does not work.

On-board LEDs

LED glows depending on various signals in firmware or pins of CPLD. Additionally to test I2C to GPIO output registers S1 push button can be used to display GPIO_output[7:0] register on LEDs. If S1 is pushed, ULED1 to ULED7 display GPIO_output[7:0] register. PHY_LED1/PHY_LED1_A and PHY_LED2/PHY_LED2_A are RJ45 connector right LED and RJ45 connector left LED respectively. These LEDs are using to display states of PGOOD, NOSEQ and EN_FMC signals.

RJ45 Connector LEDDesignatorLED StatusConditionDescription

PHY_LED1 (Green LED Anode, Yellow LED Cathode) ,

PHY_LED1_A(Green LED Cathode, Yellow LED Anode)

J14C (Right LED)OFFPGOOD = '0', NOSEQ = '0'
ON YellowPGOOD = '0', NOSEQ = '1'
ON GreenPGOOD = '1', NOSEQ = '0'
BlinkyPGOOD = '1', NOSEQ = '1'

PHY_LED2 (Green LED Cathode , Yellow LED Anode) ,

PHY_LED2_A(Green LED Anode, Yellow LED Cathode)

J14B (Left LED)ON GreenEN_FMC = '1'Power Ok signal of EN5335QI PowerSoC is high. FMC_VADJ voltage is ok.
BlinkyEN_FMC = '0'Power Ok signal of EN5335QI PowerSoC is low. FMC_VADJ voltage is faulty.
LEDDesignatorConnected to Port / SignalConditionConnected to Port / SignalConditionDescription
ULED1D6GPIO_output(0)S1 = '0' (S1 push button is pushed)mode0S1 = '1' (S1 is not pushed)

mode0 = '1' , If CM1(S3-1)= OFF and CM0(S3-2)= OFF  FMC_VADJ = 1.8V

ULED2D7GPIO_output(1)S1 = '0' (S1 push button is pushed)mode1S1 = '1' (S1 is not pushed)mode1 = '1' , If CM1(S3-1)= ON and CM0(S3-2)= OFF  FMC_VADJ = 2.5V
ULED3D8GPIO_output(2)S1 = '0' (S1 push button is pushed)mode2S1 = '1' (S1 is not pushed)mode2 = '1' , If CM1(S3-1)= OFF and CM0(S3-2)= ON  FMC_VADJ = 3.3V
ULED4D9GPIO_output(3)S1 = '0' (S1 push button is pushed)mode3S1 = '1' (S1 is not pushed)mode3 = '1' , If CM1(S3-1)= ON and CM0(S3-2)= ON   FMC_VADJ = 1.8V
ULED5D4GPIO_output(4)S1 = '0' (S1 push button is pushed)S2 button (Reset)S1 = '1' (S1 is not pushed)If LED is ON --> S2 Reset push button is pushed.
ULED6D15GPIO_output(5)S1 = '0' (S1 push button is pushed)SD_DETECTS1 = '1' (S1 is not pushed)If LED is ON --> MODE = '1' (QSPI boot mode) else MODE = '0' (SD card boot mode)
ULED7D14GPIO_output(6)S1 = '0' (S1 push button is pushed)Module UART0-RXS1 = '1' (S1 is not pushed)
ULED8D5GPIO_output(7)S1 = '0' (S1 push button is pushed)Module UART0-TXS1 = '1' (S1 is not pushed)

I2C to GPIO registers access methods

I2C to GPIO subsystem has 4 output and 4 input 8 bit registers. These registers can be written or read in linux or FSBL code as shown in the following tables:

GPIO input registersAddressRead Command in LinuxRead Command in FSBL Description
GPIO_input[7:0]0x00
i2cget -y 0 0x30 0x00
iic_read8(0x30,0x00,&data)
0x30 is device address. ( I2C to GPIO address).
GPIO_input[15:8]0x01
i2cget -y 0 0x30 0x01
iic_read8(0x30,0x01,&data)
0x30 is device address. ( I2C to GPIO address).
GPIO_input[23:16]0x02
i2cget -y 0 0x30 0x02
iic_read8(0x30,0x02,&data)
0x30 is device address. ( I2C to GPIO address).
GPIO_input[31:24]0x03
i2cget -y 0 0x30 0x03
iic_read8(0x30,0x03,&data)
0x30 is device address. ( I2C to GPIO address).
GPIO output registersAddressWrite Command in LinuxWrite Command in FSBLDescription
GPIO_output[7:0]0x00
i2cset -y 0 0x30 0x00 <data>
iic_write8(0x30,0x00,data)
0x30 is device address. ( I2C to GPIO address). 0x00 is register address.
GPIO_output[15:8]0x01
i2cset -y 0 0x30 0x01 <data>
iic_write8(0x30,0x01,data)
0x30 is device address. ( I2C to GPIO address). 0x01 is register address.
GPIO_output[23:16]0x02
i2cset -y 0 0x30 0x02 <data>
iic_write8(0x30,0x02,data)
0x30 is device address. ( I2C to GPIO address). 0x02 is register address.
GPIO_output[31:24]0x03
i2cset -y 0 0x30 0x03 <data>
iic_write8(0x30,0x03,data)
0x30 is device address. ( I2C to GPIO address). 0x03 is register address.

I2C to GPIO registers

GPIO_input bitPort/SignalDescription
0VID0EN5335QI Power SoC  Voltage Select Line 0
1VID1EN5335QI Power SoC  Voltage Select Line 1
2VID2EN5335QI Power SoC  Voltage Select Line 2
3USB_OCUSB Over Current
4USR0DIP Switch S4-A
5USR1DIP Switch S4-B
6USR2DIP Switch S4-C
7USR3DIP Switch S4-D
GPIO input bitPort/SignalDescription
8CM0(S3-2)DIP Switch S3-B
9CM1(S3-1)DIP Switch S3-A
10MIO10I2C-SCL
11MIO11I2C-SDA
12MIO12
13MIO13
14MIO14UART0-RX
15MIO15UART0-TX
GPIO input bitPort/SignalDescription
16NOSEQ
17PGOOD
18SD_WP
19SD_DETECT
20S1 User Button
21POK_FMCFMC VADJ Power Good 
22ACBUS4
23ACBUS5
GPIO input bitPort/SignalDescription
24Y0
25Y1
26Y2
27Y3
28Y4
29Y5
30Y6
31X6
GPIO output registerPort / SignalConditionDescription
GPIO_output [7:0]ULEDsS1 (User push button) = ON (pushed)To test GPIO_output it is helpful to check the sent data via i2c to GPIO on the ULEDs.
GPIO_output [15:8]vir_usr1GPIO_output[15:8] = 0x00 → vir_usr1 = '0' 
GPIO_output[15:8] = 0x01 → vir_usr1 = '1' 

This register is used to control NOSEQ pin for PCB REV03. If no access to TE0715 CPLD  or access to TE0715 CPLD  jed file is programmed on the CPLD of carrier board and CM0(S3-2) and CM1(S3-1) are OFF:
vir_usr1 = '1' → NOSEQ = '0' *
vir_usr1 = '0' → NOSEQ = '1' *

GPIO_output [23:16]vir_usr2

GPIO_output[23:16] = 0x00 → vir_usr2 = '0' 
GPIO_output[23:16] = 0x01 → vir_usr2 = '1' 

This register is used to control PGOOD pin for PCB REV03. If no access to TE0715 CPLD or access to TE0715 CPLD jed file is programmed on the CPLD of carrier board and CM0(S3-2) and CM1(S3-1) are OFF:

vir_usr2 = '1' → PGOOD= '0' *
vir_usr2 = '0' → PGOOD = '1' *

GPIO_output [31:24]-------------

*Note: This is only valid for PCB REV03. For PCB REV04 vir_usr1,vir_usr2 and vir_usr3 are not be used. For PCB REV04 PGOOD and NOSEQ can be controlled via USR2 and USR1 dip switches respectively. 

Appx. A: Change History

Revision Changes

REV02 to REV03

  • JTAG timing correction

  • Renaming ports according to the schematic REV04

  • RGPIO is removed.

  • I2C to GPIO sub system is added for communication between FPGA on the module and CPLD on the carrier board. (MIO10 --> SCL , MIO11 --> SDA)

  • Access to CPLD chip of TE0715 either via USR0 Dip switch for PCB REV04 or via  CM0 and CM1 for PCB REV03 revisions

  • In PCB REV04 USR0 is used to access to TE0715 CPLD

  • In PCB REV04 USR1 is used to change NOSEQ signal, if no access to TE0715 CPLD is active (USR0 = OFF)

  • In PCB REV04 USR2 is used to change PGOOD, if no access to TE0715 CPLD is active (USR0 = OFF)

  • In PCB REV04 USR3 is used to change JTAGMODE signal of CPLD of module. USR3 = OFF --> Access to FPGA , USR3 = ON --> Access to CPLD of module

  • In PCB REV03 CM0 and CM1 dip switches are used to access to CPLD of TE0715 or other modules.

  • Displaying PGOOD and NOSEQ signal states on PHY_LED1/PHY_LED1_A

  • Displaying state of POK_FMC  ( power ok signal of EN5335QI PowerSoC) on PHY_LED2/PHY_LED2_A

REV01 to REV02

  • Power Management
    • VADJ is switchable by S3 dip switches
  • Reset Management
    • only little changes
  • RGPIO Interface to FPGA
    • RGPIO support
  • LED
    • new Order and accessible by RGPIO
  • Module CPLD access is possible know

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.


DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

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REV03REV03, REV04

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  • REV03 release
  • Firmware release (SC-PGM-TE0705-PCB_REV0304-CARRIER-CPLD_REV03-20230329.zip)
  • I2C to GPIO added
  • RGPIO removed
  • ULEDs and PHY_LEDs function changed

2017-06-08

v.34

REV02REV03,REV04

John Hartfiel

document style update
2016-11-17

v.27


REV02REV03, REV04John HartfielRevision 02 finished
2016-11-04


v.1

---

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Initial release

All

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Appx. B: Legal Notices

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.


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