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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/TE0715TE0600
Trenz Electronic GigaBee XC6SLX series are industrial-grade FPGA micromodules integrating a leading-edge Xilinx Spartan-6 LX FPGA, Gigabit Ethernet transceiver (physical layer), two independent banks of 16-bit-wide 128/512 MBytes DDR3 SDRAM, 16 MBytes SPI Flash memory for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via robust board-to-board (B2B) connectors.

All this on a tiny footprint, smaller than half a credit card, at the most competitive price.

Block diagram

Image Added

Block diagram of the GigaBee XC6SLX board(warning) to do (warning)

Main components

Image Removed Image Removed

   1. Zynq-7000 all programmable SoC.

   2. System controller CPLD.

   3. Programmable clock generator.

Image AddedImage Added

Top side:

...

  • Xilinx Spartan-6 LX FPGA
  • clock generator

...

  • 10/100/1000 Mbps

...

  • Ethernet PHY
  • protected 1-Wire EEPROM
  • DDR3-SDRAM

...

   6. Hi-Speed USB 2.0 ULPI transceiver.

   7a. B2B connector JM1.

   7b. B2B connector JM2.

   7c. B2B connector JM3.

   8. 256 Mbit (32 Mbyte) 3.0V SPI flash memory.

   9. Low power RTC with battery backed SRAM.

   10. PowerSoC DC-DC converter.

  • DC-DC converters

Bottom side:

  • B2B connector J1
  • B2B connector J2
  • Flash memory

Key features

  • Industrial-grade Xilinx

    Zynq-7000 (XC7Z015, XC7Z030) SoM
  • Rugged for shock and high vibration
  • 2 × ARM Cortex-A9
  • 10/100/1000 tri-speed gigabit Ethernet transceiver PHY
  • MAC address EEPROM
  • 32-Bit wide 1GB DDR3 SDRAM
  • 32 MByte QSPI flash memory
  • Programmable clock generator
    • Transceiver clock (default 125 MHz)

  • Spartan-6 LX FPGA micromodule (LX45 / LX100 / LX150)

  • 10/100/1000 tri-speed Gigabit Ethernet transceiver (PHY)

  • 2 x 16-bit-wide 1 Gb (128 MB) or 4 Gb (512 MB) DDR3 SDRAM

  • 128 Mb (16 MB) SPI Flash memory (for configuration and operation) accessible through:

  • 1 kb protected 1-Wire EEPROM with SHA-1 Engine

  • JTAG port (SPI indirect)

  • FPGA configuration through:

    • B2B connector

    • JTAG port

    • SPI Flash memory

  • Plug-on module with 2 × 100

    Plug-on module with 2 × 100-pin and 1 × 60

    -pin high-speed hermaphroditic strips

  • 132

    Up to 52 differential, up to 109 single-ended (+ 1 dual-purpose) FPGA I/

    Os (65 LVDS pairs possible) and 14 PS MIO

    O pins available on B2B

    connectors
  • 4 GTP/GTX (high-performance transceiver) lanes
    • GTP/GTX (high-performance transceiver) clock input
  • USB 2.0 high-speed ULPI transceiver
  • On-board high-efficiency DC-DC converters
    • 4.0 A x 1.0 V power rail
    • 1.5 A x 1.5 V power rail
    • 1.5 A x 1.8 V power rail

  • strips

  • 4.0 A x 1.2 V power rail

  • 1.5 A x 1.5 V power rail

  • 125 MHz reference clock signal

  • Single-ended custom oscillator (option)

    System management

  • eFUSE bit-stream encryption

  • AES bit-stream encryption
  • Temperature compensated RTC (real-time clock)

  • (LX100 or larger)

  • 1 user

    User

    LED

  • Evenly-spread supply pins for good signal integrity

Additional assembly options are available for cost or performance optimization upon request.

Initial Delivery State

Storage device name

Content

Notes

24AA025E48 EEPROM

User content not programmed

Valid MAC Address from manufacturer.

SPI Flash

OTP Area

Empty, not programmed

Except serial number programmed by flash vendor.

SPI Flash Quad Enable bit

Programmed

-

SPI Flash main array

Demo design

-

EFUSE USER

Not programmed

-

EFUSE Security

Not programmed

-

Interfaces and Pins

Board to Board (B2B) I/O's

I/O signals connected to the SoC's I/O bank and B2B connector: 

...

13

...

HR

...

JM1

...

48

...

User

...

34

...

HR/HP

...

JM2

...

18

...

User

...

TE0715-xx-15 has no HP-Banks, Banks 34 and 35 are HR-Banks at this module!

Banks 34 and 35 of TE0715-xx-30 are HP-Banks and  support voltages from 1.2V to 1.8V standards

...

HR/HP

...

JM2

...

50

...

User

...

34

...

HR/HP

...

JM3

...

16

...

User

...

500

...

MIO

...

JM1

...

8

...

3.3V

...

501

...

MIO

...

JM1

...

6

...

1.8V

...

112

...

GT

...

JM3

...

4 Lanes

...

N/A

...

112

...

GT CLK

...

JM3

...

One Differential Input

...

N/A

...

NB! AC coupling capacitors

on baseboard required.

For detailed information about the pin out, please refer to the Master Pinout Table. 

Default MIO Mapping

MIOFunctionB2B PinNotes MIOFunctionB2B PinNotes
0GPIOJM1-87B2B 16..27ETH0-RGMII
1QSPI0-SPI Flash-CS 28..39USB0-ULPI
2QSPI0-SPI Flash-DQ0 40SDIO0JM1-27B2B
3QSPI0-SPI Flash-DQ1 41SDIO0JM1-25B2B
4QSPI0-SPI Flash-DQ2 42SDIO0JM1-23B2B
5QSPI0-SPI Flash-DQ3 43SDIO0JM1-21B2B
6QSPI0-SPI Flash-SCK 44SDIO0JM1-19B2B
7GPIO-Green LED D4 45SDIO0JM1-17B2B
8QSPI0-SPI Flash-SCKFB 46GPIO-

Ethernet PHY LED2

INTn Signal.

9 JM1-91B2B 47GPIO-RTC Interrupt
10 JM1-95B2B 48I2C1-SCL on-board I2C
11 JM1-93B2B 49I2C1-SDA on-board I2C
12 JM1-99B2B 50GPIO-ETH0 Reset
13 JM1-97B2B 51GPIO-USB Reset
14UART0JM1-92B2B 52ETH0-MDC
15UART0JM1-85B2B 53ETH0-MDIO

Gigabit Ethernet

On board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII Interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an onboard 25MHz oscillator (U9), the 125MHz output clock is connected to IN5 of the PLL chip (U10).

Ethernet PHY connection

...

Can be routed via PL to any free PL I/O pin in B2B connector.

This LED is connected to PL via level-shifter implemented in

system controller CPLD.

...

By default the PHY address is strapped to 0x00, alternate

configuration is possible.

...

USB Interface

USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied from an onboard 52MHz oscillator (U15).

USB PHY connection

...

memory

Blinky Demo

 

protected 1-Wire EEPROM

not programmed

 

Power Consumption

Power consumption of GigaBee XC6SLX modules highly depend on the FPGA design implemented. Some typical power consumptions are provided below for the following reference systems:

  • Boards – GigaBee XC6SLX 45/100/150

  • Base board – TE0603-02

  • Power supply – 5 V from baseboard

  • Connected Gigabit Ethernet cable

FPGA typeUnconfiguredConfigured with Web-server reference design
LX450.15 A0.6 A
LX1000.17 A0.5 A
LX1500.2 A0.5 A

Detailed Description

Power Supply

The nominal supply voltage of the GigaBee XC6SLX is 3.3 volt. The minimum supply voltage is 3.0 volt. The maximum supply voltage is 3.45 volt.

Warning
titleWarning

Supply voltages beyond the range might affect to device reliability, or even cause permanent damage of the device!

Board power supply diagram

Image Added

Power Supply Sources

GigaBee XC6SLX board must be powered at least in one of the following two ways:

  • through B2B connector J1 (pins 1, 3, 5, 7, 9, 11, 13, 15),
  • through B2B connector J2 (pins 2, 4, 6, 8, 10, 12).

We recommend to supply the module with all these 14 pins. When one or more of these pins are not power supplied, it or they can be used as power source for user applications.

Please make sure that your logic design does not draw more RMS current per pin than specified in section Board-to-board Connectors.

FPGA banks VCCIO power supply

FPGA VCCIO power options are shown below. Default values for configurable voltages are shown in braces.

BankSupply voltage
B0

VCCIO 0 (3.3 V)

B1VCCIO 1 (1.5 V)
B23.3 V
B31.5 V

Bank 0 power supply VCCIO 0 can be configured by user to 3.3 V, 2.5 V or 1.5 V, see Chapter VCCIO0 Power Rail. Bank 1 VCCIO supply voltage is configured to 1.5 V to communicate with DDR3 SDRAM memory chip.

By special request, modules can be supplied without DDR3 SDRAM chips. Contact Trenz Electronic support for details.

On-board Power Rails

GigaBee XC6SLX has the following power rails on-board.

3.3V Power Rail

It is the main internal power rail and must be supplied from an external power source.

It supplies the other following power rails:

  • 1.2V / 4 A on-board high-efficiency switching voltage regulator;
  • 1.5V / 1.5 A on-board high-efficiency switching voltage regulator;
  • 2.5V 0.8 A linear voltage regulator;
  • VCCIO0 power rail (option) (if zero-resistor R80 is not populated and zero-resistor R79 is populated).
1.2V Power Rail

It is converted from the 3.3V rail by a switching voltage regulator and can provide up to 4.0 A to:

  • FPGA VCCINT power supply pins;
  • Ethernet PHY;
  • J1 connector.
1.5V Power Rail

It is converted from the 3.3V rail by a switching voltage regulator and can provide up to 1.5 A to:

  • DDR3 SDRAM;
  • Vref1 / Vref2 DDR3 SDRAM reference voltages;
  • FPGA bank 3 VCCO;
  • J1 connector.
2.5V Power Rail

It is converted from the 3.3V rail by a linear voltage regulator and can provide up to 0.8 A to:

  • VCCAUX power rail;
  • Ethernet physical layer;
  • J1 connector;
  • J2 connector (option: if zero-resistor R80 is populated and zero-resistor R79 is not populated).
VCCAUX Power Rail

It is converted from the 3.3V rail by a linear voltage regulator and can provide up to 0.8 A to:

  • FPGA auxiliary circuits;
  • J2 connector.
VCCIO0 Power Rail

There are 4 options to supply this rail:

  1. from 3.3 V power rail (if zero-resistor R79 is populated1 and R80 is not);
  2. from 2.5 V power rail (if zero-resistor R80 is populated and R79 is not);
  3. from 1.5 V power rail (if zero-resistors R79 and R80 are not populated and VCCIO0 connected to 1.5 V power rail);
  4. from an external power source through J2 B2B connector (pins 1, 3, 5, 7, 9) (if R79 and R80 are not populated)

It supplies:

  • FPGA bank 0 VCCO.

Figure below show simplified schematic of power options. Dashed resistors are not populated by default.

Image Added

Table below summarizes power rails information.

power-rail
name

nominal
voltage(V)

maximum
current (A)

power
source

system
supply

user
supply

3.3V3.3

2.4
(3.3 option)

J1, J2module

J1 (≤1.2 A)
J2 (≤1.2 A,
≤2.1 option)

2.5V2.50.83.3V ? linearEthernet

J1 (≤0.3 A)
J2 (option)

1.5V1.51.53.3V ? switch

DDR3 SDRAM
VCCO (1+3)

J1 (≤0.3 A)
1.2V1.24.03.3V ? switch

VCCINT
Ethernet

J1 (≤0.6 A)
VCCAUX2.50.83.3V ? linearFPGAJ2 (≤0.3 A)
VCCCIO01.2, 1.5, 1.8, 2.5, 3.30.9J2VCCO (0)J2 (≤0.9 A)

Power Supervision

Power-on Reset

During power-on, the /RESET line is first asserted. Thereafter, the supply voltage supervisor monitors the power supply rail 3.3V and keeps the /RESET line active (low) as long as the supply rail remains below the threshold voltage (2.93 volt). An internal timer delays the return of the /RESET line to the inactive state (high) to ensure proper system reset prior to a regular system start-up. The typical delay time td of 200 ms starts after the supply rail has risen above the threshold voltage.

Image Added

After this delay, the /RESET line is reset (high) and the FPGA configuration can start. When the supply rail voltage drops below the threshold voltage, the /RESET line becomes active (low) again and stays active (low) as long as the rail voltage remains below the threshold voltage (2.93 volt). Once the rail voltage raises again and remains over the threshold voltage for more than the typical delay time td of 200 ms, the /RESET line returns to the inactive state (high) to allow a new system start-up.

Image Added

Power Fail

GigaBee XC6SLX integrates a power-fail comparator which can be used for low-battery detection, power-fail warning, or for monitoring a power supply other than the main supply 3.3 V. When the voltage of the PFI (power-fail comparator input, input pin 16 of connector J2) line drops below 1.25 volt, the /PFO (power-fail comparator output, FPGA pin A2, label IO_L83P_3) line becomes active (low). The user application can sense this line to take action. To set a power fail threshold higher than 1.25 volt, the user can implement a simple resistive voltage divider on the carrier board.

Board-to-board Connectors

Include Page
IN:Samtec LSHM
IN:Samtec LSHM

EPROM

GigaBee XC6SLX board contains a Maxim DS2502-E48 node address chip with factory-programmed valid MAC-48 address and 768 bits of OTP-EPROM memory for user data.

Address chip provide convenient data access through 1-Wire interface up to 16.3 kbps (FPGA pin T11).

More information can be found in the Maxim DS2502-E48 product overwiew.

Additional 1Kb protected 1-Wire EEPROM with SHA-1 engine DS2432 accessible via the same line.

More information can be found at the Maxim DS2432 product page.

DDR3 SDRAM Memory

The board contains two 1 Gb (128 MB) or 4 Gb (512 MB) DDR3 SDRAM chips. Data width of each chip is 16 bit. DDR3 memory connected to FPGA bank 1 and FPGA bank 3. Spartan-6 Memory controller Blocks operations can be merged to implement effective 32-bit memory interface. Refer Xilinx XAPP496 for detailed information.

Flash Memory

GigaBee XC6SLX board contains 128 Mb (16 MB) serial flash memory chip Winbond W25Q128FV (W25Q128BV till REV 02) (U11). This serial flash chip can operate as general SPI memory mode and in double or quad modes. Usage of dual and quad modes increase bandwidth up to 40 MB/s.

For more information see Winbond W25Q128FV (W25Q128BV till REV 02) product overview.

Flash can be programmed in several ways:

  • Direct SPI programming via J1 connector.
  • Indirect SPI programming via FPGA pins, controlled by JTAG.
  • Direct SPI programming by FPGA, using SPI core.

Serial flash is connected to FPGA bank 2 and B2B connector J1; used pins are listed in the table below.

Flash signalFPGA pinJ1 pin
/CST587
CLKY2191
DI(IO0)AB2095
DO(IO1)AA2093
/WP(IO2)U1499
/HOLD(IO3)U1397

Serial flash signals connection

Ethernet

The board contains a Marvell Alaska Ethernet PHY chip (88E1111) operating at 10/100/1000 Mb/s. The board supports GMII interface mode with the FPGA. Configuration details:

  • PHY address – 00111
  • Do not advertise the PAUSE bit
  • Auto Neg
  • Advertise all caps
  • Prefer slave
  • Auto crossover
  • 125clk - enabled
  • GMII to copper
  • Fiber auto-detect - disabled
  • Sleep mode - disabled

Ethernet signals from PHY are connected to B2B connector J1. To use Ethernet in your design, GigaBee module should be connected to the carrier board, which have Ethernet magnetics and RJ45 connector. TE0603 carrier board can be used to access Ethernet capabilities of GigaBee XC6SLX series modules.

Note
titleCaution

For correct operation of the Marvell PHY it is required that PHY Reset pin sees valid low level each time power is applied and also during any brownout situations where system Power is removed for short time, but some pins are not at valid logic levels.

Solutions:

  1. if GbE PHY is not used PHY reset pin can be tied off to GND
  2. if PLL is used from PHY clock, then PLL "locked" output can be used to reset PHY - as long PLL is not locked, it will keep PHY in reset
  3. Reset pulse generation circuit clocked from FPGA internal configuration clock, this circuit can force PHY reset pin to low when external clock from PHY is not available
  4. any custom Reset circuit that is guaranteed to drive PHY reset to low level at least once after FPGA configuration when PHY clock is not running.
  5. any user logic that is guaranteed to drive PHY reset low after FPGA configuration (without using PHY clock).

Explanation: Marvell PHY samples the MODE pins ONLY when it sees low level on PHY reset input, it does not sample those pins during short power off situations (if the reset pin holds high level because of pin capacitance and high impedance of the pins)! So it is possible that the PHY mode is reset, but the mode pins are not sampled again - this yields in mode setting where 125MHz reference clock from PHY is not available.

Oscillators

The module has one 25 MHz oscillator for Ethernet PHY (U9). Ethernet PHY provides clock multiplication and resulting 125 MHz clock acts as a system and user clock for the FPGA (FPGA input pin AA12).

Note
titleCaution

Note: For correct generation start, PHY should receive reset pulse. Recommended way to do it it's to connect PHY reset signal  (ETHERNET_PHY_RST_N) to LOCKED output of corresponding DCM (DCM which use 125 MHz from PHY).

The module also provides the footprint for custom 3.3 V single-ended oscillator (U12) which can be installed as an option (FPGA input pin Y13).

User LED

The module contains one user active-low LED connected to FPGA output pin T20. To access more LEDs, use a carrier board and drive FPGA signals connected to B2B connectors. As LED connected to FPGA bank with configurable VCCIO to light LED FPGA pin should in '0' (low) state. To disable LED FPGA pin should be in 'Z' (High impedance).

Watchdog

GigaBee XS6LX has a watchdog timer that is periodically triggered by a positive or negative transition of the WDI (watchdog input) line (FPGA pin V9). When the supervising system fails to re-trigger the watchdog circuit within the time-out interval (min 1.1 s, typ 1.6 s, max 2.3 s), the /WDO (watchdog output) line becomes active (low). This event also re-initializes the watchdog timer.

If zero-resistors R2 is not assembled, the watchdog is disabled (alternate assembly).

If zero-resistors R2 is assembled, the watchdog can be enabled (standard assembly). In this case there is still two options:

To enable the watchdog, after module power-up, drive the WDI signal to generate at least one transition (no matter positive or negative).

To keep watchdog disabled, set WDI FPGA signal output to high-impedance. One way to reach this goal is to leave FPGA pin V9 (label IO_L50N_2) undeclared in user constrains file (UCF) and set “unused IOB pins” to “float” in the Xilinx Project Navigator options, see Fig. below.

(Project properties > Configuration options > Unused IOB Pins > Float).

Image Added

Unused IOB Pins option selection.

 

In the standard assembly, the /WDO (watchdog output) line is left unconnected1 and the only possibility to reset the module is by driving the /MR (master reset) line active (low) through pin 18 of connector J2.

In the alternate assembly, the /WDO (watchdog output) line is connected through zero-resistor R3 to /MR (master reset) line.

Note
titleCaution

If alternate assembly is used, pin 18 of connector J2 must be left unconnected.

Configuration Options

The FPGA on GigaBee XC6SLX board can be configured by means of the following devices:

  • Xilinx download cable (JTAG)
  • SPI Flash memory

JTAG Configuration

The FPGA can be configured through the JTAG interface. JTAG signals are connected to B2B connector J2. When GigaBee XC6SLX board is used with the TE0603 carrier board, the JTAG interface can be accessed via connectors J5 and J6 on the carrier board.

Flash Configuration

Default configuration option for FPGA is “Master Serial/SPI”. The bit-stream for the FPGA is stored in a serial Flash chip (U11). See chapter 2.7 Flash Memory for additional information.

eFUSE Programming

eFUSE programming feature is not directly supported by GigaBee XC6SLX modules, but it is possible to use it. To program eFUSE, please follow the steps below:
  • Connect VCCAUX to 3.3V power rail.
    On TE0603 it can be done by connecting J5 pin 2 or J6 “VREF” (VCCAUX) to J1 any pin from 1,2,3,4 (3.3V). See Figure below.
  • Program eFUSE using JTAG cable and iMPACT software.
  • Remove power supply connections to VCCAUX

Image Added

B2B Connectors Pin Descriptions

This section describes how the various pins on B2B connectors J1 and J2 connects to TE0600 on-board components. There are five main signal types connected to B2B connectors:

  • FPGA users signals;
  • FPGA system signals;
  • Power signals;
  • Ethernet PHY signals;
  • Other system signals.
FPGA BankSingle-endedDifferentialTotalVCCIO
Bank 012245VCCIO 0 (3.3 V)
Bank 11613VCCIO 1 (1.5 V)
Bank 2321453.3 V
Bank 30361.5 V
 552109 

B2B signals count

Pin Labeling

FPGA user signals connected to B2B connectors are characterized by the "B2B_Bx_Lyy_p" naming convention, where:

  • B2B defines a "FPGA to B2B" signal type;
  • Bx defines the FPGA bank (x = bank number);
  • Lyy defines a differential pair or signal number (yy = pair number);
  • p defines a differential signal polarity (P = positive, N = negative); single ended signals do not have this field.

Ethernet PHY signals use "PHY_name" naming conversions where "PHY" defines signal type "PHY to B2B" and "name" is PHY signal name.

Remaining signals use custom names.

Pin Numbering

Note that GigaBee XC6SLX have hermaphroditic B2B connectors. A feature of  hermaphroditic connector numbering is that connected signal numbers don't match. Odd signals on module connect to even signals on baseboard. For example module signal 1 to baseboard signal 2, module signal 2 to baseboard signal 1, module signal 3 to baseboard signal 4 and so on.

Pin Types

Most pins of B2B connectors J1 and J2 are general-purpose, user-defined I/O pins (GPIOs). There are, however, up to 8 different functional types of pins on the TE0600, as outlined in Table below. In pin-out tables Table 11 and Table 12, the individual pins are colour-coded according to pin type as in Table below.

 

Image Added

TE0600 pin types

type
colour code		description
DIOUnrestricted, general-purpose differential user-I/O pin.
SIOUnrestricted, general-purpose user-I/O pin.
CONFIGDedicated configuration signals.
PWRMGMTControl and status signals for the power-saving Suspend mode.
JTAGDedicated JTAG signals.
GNDDedicated ground pin. All must be connected.
TETrenz Electronic specific pin type.
See the description of each pin in the user manual for additional information on the corresponding signals.
POWPower signals.
SPISPI signals.
PHYEthernet PHY signals.

Note that some of Spartan-6 I/O types are partially compatible, so pins of compatible types can be used as inputs for signal of other type. For example pins from FPGA bank with 1.5V VCCO (IOSTANDARD = LVCMOS15) can be used as inputs for 1.2V, 1.8V, 2.5V and 3.3V signals.

See “Spartan-6 FPGA SelectIO Resources” page 38 for detailed information.

External Bank 2 differential clock connection

TE0600-02 module have optional connection to FPGA bank 2 differential clock input pins. To provide connection from B2B_B2_L41_P signal to Y13 FPGA pin, zero-resistor R69 should be soldered. To provide connection B2B_B2_L41_N signal to AB13 FPGA pin, zero-resistor R81 should be soldered. Note that in this case optional user oscillator U13 can't be used.

J1 Pin-out

Image Added

J1 pin-out

J1 pinNetType

FPGA pin

Net LengthJ1 pinNetTypeFPGA pinNet Length
13.3VPOW--2GNDGND--
33.3VPOW--4PHY_MDI0_PPHY--
53.3VPOW--6PHY_MDI0_NPHY--
73.3VPOW--8GNDGND--
93.3VPOW--10PHY_MDI1_PPHY--
113.3VPOW--12PHY_MDI1_NPHY--
133.3VPOW--14PHY_AVDDPHY--
153.3VPOW--16PHY_MDI2_PPHY--
17PHY_L10PHY--18PHY_MDI2_NPHY--
19PHY_L100PHY--20GNDGND--
21PHY_L1000PHY--22PHY_MDI3_PPHY--
23PHY_DUPPHY--24PHY_MDI3_NPHY--
25PHY_LED_TXPHY--26GNDGND--
27PHY_LED_RXPHY--28ENTE--
29GNDGND--30INITCONFIGT6-
31B2B_B2_L57_NDIOAB48.66mm32B2B_B2_L32_NSIOAB118.12mm
33B2B_B2_L57_PDIOAA49.84mm34GNDGND--
35B2B_B2_L49_NDIOAB68.66mm36B2B_B2_L60_PDIOT79.96mm
37B2B_B2_L49_PDIOAA69.58mm38B2B_B2_L60_NDIOR711.16mm
392.5VPOW--40B2B_B2_L59_NDIOR811.42mm
411.2VPOW--42B2B_B2_L59_PDIOR911.36mm
431.2VPOW--44GNDGND--
45B2B_B2_L48_NDIOAB79.98mm46B2B_B2_L44_NDIOY1011.34mm
47B2B_B2_L48_PDIOY710.98mm48B2B_B2_L44_PDIOW1010.21mm
49B2B_B2_L45_NDIOAB810.60mm50B2B_B2_L42_NDIOW117.52mm
51B2B_B2_L45_PDIOAA811.053mm52B2B_B2_L42_PDIOV118.36mm
53GNDGND--54GNDGND--
55B2B_B2_L43_NDIOAB913.75mm56B2B_B2_L18_PDIOV137.94mm
57B2B_B2_L43_PDIOY912.97mm58B2B_B2_L18_NDIOW136.96mm
59B2B_B2_L41_NDIOAB10, AB1310.33mm60B2B_B2_L8_NDIOU169.92mm
61B2B_B2_L41_PDIOAA10, Y1311.01mm62B2B_B2_L8_PDIOU179.94mm
63GNDGND--64GNDGND--
65B2B_B2_L21_PDIOY1513.12mm66B2B_B2_L11_PDIOV178.31mm
67B2B_B2_L21_NDIOAB1512.37mm68B2B_B2_L11_NDIOW177.29mm
69B2B_B2_L15_PDIOY1714.20mm70B2B_B2_L6_PDIOW187.40mm
71B2B_B2_L15_NDIOAB1713.77mm72B2B_B2_L6_NDIOY186.94mm
73GNDGND--74GNDGND--
75B2B_B2_L31_NSIOAB1212.30mm76B2B_B2_L5_PDIOY196.18mm
77SUSPENDSYSN1519.23mm78B2B_B2_L5_NDIOAB196.12mm
79VBATTCONFIGR17-80B2B_B2_L9_NDIOV188.43mm
81VFSCONFIGP16-82B2B_B2_L9_PDIOV198.36mm
83RFUSECONFIGP15-84GNDGND--
85AWAKESYST1914.15mm86B2B_B2_L4_NDIOT1711.88mm
87CSO_BSPIT5-88B2B_B2_L4_PDIOT1811.96mm
89GNDGND--90GNDGND--
91CCLKSPIY21-92B2B_B2_L29_NSIOY1213.58mm
93MISOSPIAA20-94B2B_B2_L10_NDIOR1517.01mm
95MOSISPIAB20-96B2B_B2_L10_PDIOR1616.97mm
97MISO3SPIU13-98B2B_B2_L2_NDIOAB215.06mm
99MISO2SPIU14-100B2B_B2_L2_PDIOAA216.19mm

J2 Pin-out

Image Added

J2 Pin-out

J2 pinNetTypeFPGA pinNet LengthJ2 pinNetTypeFPGA pinNet Length
1VCCIO0POW--23.3VPOW--
3VCCIO0POW--43.3VPOW--
5VCCIO0POW--63.3VPOW--
7VCCIO0POW--83.3VPOW--
9VCCIO0POW--103.3VPOW--
11B2B_PROGBCONFIG--123.3VPOW--
13HSWAPENCONFIGA3-14B2B_B0_L1SIOA49.017mm
15B2B_B3_L60_NDIOB15.44mm16PFITE--
17B2B_B3_L60_PDIOB25.27mm18/MRTE--
191.5VPOW--20GNDGND--
21B2B_B3_L9_NDIOT319.36mm22B2B_B0_L2_PDIOC510.17mm
23B2B_B3_L9_PDIOT418.76mm24B2B_B0_L2_NDIOA59.60mm
25B2B_B0_L3_PDIOD66.76mm26B2B_B0_L4_NDIOA67.65mm
27B2B_B0_L3_NDIOC65.66mm28B2B_B0_L4_PDIOB68.71mm
29GNDGND--30GNDGND--
31B2B_B3_L59_PDIOJ711.90mm32B2B_B0_L5_NDIOA78.59mm
33B2B_B3_L59_NDIOH811.71mm34B2B_B0_L5_PDIOC79.54mm
35B2B_B0_L32_PDIOD76.93mm36B2B_B0_L6_NDIOA87.42mm
37B2B_B0_L32_NDIOD86.87mm38B2B_B0_L6_PDIOB88.43mm
39GNDGND--40GNDGND--
41B2B_B0_L7_NDIOC86.62mm42B2B_B0_L8_NDIOA99.28mm
43B2B_B0_L7_PDIOD96.71mm44B2B_B0_L8_PDIOC99.92mm
45B2B_B0_L33_NDIOC105.66mm46B2B_B0_L34_NDIOA107.58mm
47B2B_B0_L33_PDIOD106.76mm48B2B_B0_L34_PDIOB108.60mm
49GNDGND--50GNDGND--
51B2B_B0_L36_PDIOD116.76mm52B2B_B0_L35_NDIOA118.89mm
53B2B_B0_L36_NDIOC125.87mm54B2B_B0_L35_PDIOC119.92mm
55B2B_B0_L49_PDIOD146.96mm56B2B_B0_L37_NDIOA127.52mm
57B2B_B0_L49_NDIOC145.96mm58B2B_B0_L37_PDIOB128.74mm
59GNDGND--60GNDGND--
61B2B_B0_L62_PDIOD157.44mm62B2B_B0_L38_NDIOA138.38mm
63B2B_B0_L62_NDIOC166.95mm64B2B_B0_L38_PDIOC139.87mm
65B2B_B0_L66_PDIOE168.07mm66B2B_B0_L50_NDIOA147.66mm
67B2B_B0_L66_NDIOD176.96mm68B2B_B0_L50_PDIOB148.87mm
69GNDGND--70GNDGND--
71B2B_B1_L10_PDIOF169.56mm72B2B_B0_L51_NDIOA1510.22mm
73B2B_B1_L10_NDIOF178.85mm74B2B_B0_L51_PDIOC1510.67mm
75B2B_B1_L9_PDIOG1610.59mm76B2B_B0_L63_NDIOA167.95mm
77B2B_B1_L9_NDIOG1710.23mm78B2B_B0_L63_PDIOB169.12mm
79GNDGND--80GNDGND--
81B2B_B1_L21_NDIOJ1613.22mm82B2B_B0_L64_NDIOA179.55mm
83B2B_B1_L21_PDIOK1614.41mm84B2B_B0_L64_PDIOC1710.25mm
85B2B_B1_L61_PDIOL1714.89mm86B2B_B0_L65_NDIOA188.51mm
87B2B_B1_L61_NDIOK1813.59mm88B2B_B0_L65_PDIOB189.29mm
89GNDGND--90GNDGND--
91VCCAUXPOW--92B2B_B1_L20_PDIOA208.02mm
93TMSJTAGC18-94B2B_B1_L20_NDIOA217.82mm
95TDIJTAGE18-96B2B_B1_L19_PDIOB219.63mm
97TDOJTAGA19-98B2B_B1_L19_NDIOB229.06mm
99TCKJTAGG15-100B2B_B1_L59SIOP1927.19mm

Signal Integrity Considerations

Traces of differential signals pairs are routed symmetrically (as symmetric pairs).

Traces of differential signals pairs are NOT routed with equal length, although difference in signal lines length is negligible for actual signal frequencies. For applications where traces length has to be matched or timing differences have to be compensated, Tables below list the trace length of I/O signal lines measured from FPGA balls to B2B connector pins.

Traces of differential signals pairs are routed with a differential impedance between the two traces of 100 ohm. Single ended traces are routed with 60 ohm impedance.

An electronic version of these pin-out tables are available for download from the Trenz Electronic support area of the web site.

Module revisions and assembly variants

Module revision coded by 4 FPGA BR[3:0] pins, which can be read by FPGA firmware. All these pins should be configured to have internal PULLUP.

Signal
FPGA pin		BR3
R19		BR2
P18		BR1
N16		BR0
P17
Revision 011111
Revision 021110
Revision 031101

Board revisions pin coding

 

Main differences between 01 and 02 revisions:

  • More powerful regulators for 1.2V and 1.5V rails
  • VCCAUX separated from 2.5V power rail
  • 128Mbit SPI Flash
  • Additional secure 1Kbit EEPROM
  • Optional B2B connection to bank 2 differential clock input

Main differences between 02 and 03 revisions:

  • Optimized placement and routing for DC/DC converters
  • Added thermal vias to mounting holes
  • Added Testpoints
  • Changed Board revision identification to REV03
  • Changed U9 from SIT1602AI-83-33E-25.0000 to SiT8008AI-73-XXS-25.000000E
  • Added Track-it™ Traceability Pad
  • Change SPI Flash from W25Q128BVEIG to W25Q128FVEIG
  • DDR3 changed from IM4G16D3EABG-125I to IM4G16D3FABG-125I for the 4 GBit variants
  • U13 (DS2432P+) is no longer populated by default

 

Module assembly variants coded by 4 zero ohm resistors, connected to FPGA AV[3:0] pins. All these pins should be configures to have internal PULLUP.

Signal
FPGA pin		AV3
M18		AV2
M17		AV1
V20		AV0
U19		Speed
grade		SDRAMTemp
grade
TE0600-02[V|B]000022x128MBitC
TE0600-02[V|B]I000122x128MBitI
TE0600-02[V|B]F001032x128MBitC
TE0600-02[V|B]IF001132x128MBitI
TE0600-02[V|B]MF010032x512MBitC

Assembly variants pin coding

Related Materials and References

The following documents provide supplementary information useful with this user manual.

Data Sheets

Documentation Archives

User Guides

Design and Development Tools

Design Resources

Tutorials

Glossary of Abbreviations and Acronyms

(error)A WARNING notice denotes a hazard. It calls attention to an operating procedure, practice, or the like that, if not correctly performed or adhered to, could result in damage to the product or loss of important data. Do not proceed beyond a WARNING notice until the indicated conditions are fully understood and met.
(warning)A CAUTION notice denotes a risk. It calls attention to an operating procedure, practice, or the like that, if not correctly performed or adhered to, could result in a fault. (undesired condition that can lead to an error) Do not proceed beyond a CAUTION notice until the indicated conditions are fully understood and met.

API

application programming interface

B2B

board-to-board

DSP

digital signal processing; digital signal processor

EDK

Embedded Development Kit

IOB

input / output blocks; I/O blocks

IP

intellectual property

ISP

In-System Programmability

OTP

one-time programmable

PB

push button

SDK

Software Development Kit

TE

Trenz Electronic

XPS

Xilinx Platform Studio

Mechanical Dimensions

GigaBee XC6SLX can reach a minimum vertical height of about 8 mm, if B2B connectors are not assembled. The maximum component height on the module board on the top side is about 3.5 mm. The maximum component height on the module board on the bottom side is about 3.0 mm.

The typical minimum and maximum height from the carrier board surface, of a GigaBee XC6SLX when it mounted on a carrier board, is respectively about 5.0 mm and about 13 mm.

GigaBee XC6SLX has 4 mounting holes, one in each corner. The module can be fixed by screwing M3 screws (ISO 262) onto a carrier board through those mounting holes.

 

Image Added

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Weight

GigaBee XC6SLX weighs between 17.1 and 17.3 g with standard connectors.

Document Change History

Date

Revision

Contributors

Description

2011-10-010.01AIKRelease.
2011-10-050.02AIKAdded B2B pin-out section.
2011-10-060.03AIKReformatted pin-out tables. Added eFUSE programming section.
2011-10-060.04AIKAdded board photos. Additions to eFUSE section.
2011-10-060.05AIKRemoved net length information for nets which can't be measured right.
2011-10-060.06AIKAdded power consumption section.
2011-10-080.07AIKLittle fixes after FDR audit.
2011-10-120.08AIKFix in eFUSE section.
2011-11-110.09AIKAdded pin numbering description for B2B connectors
2012-01-200.10AIKAdded pin compatibility note and manual reference.
2012-04-120.11AIKAdded FPGA banks VCCIO voltages table.
2012-04-171.00FDRUpdated documentation link.
Replaced obsolete ElDesI and RedMine links with current GitHub links.
Updated dating convention.
2012-05-181.01AIKCorrected cross-reference in section 3.2. Corrected LED description.
2012-06-181.02FDRRemoved junction temperature limits under connector current ratings.
2012-07-181.03AIKAdded table with B2B signals summary per FPGA bank
2012-10-302.01AIKFork to 01 and 02 board revisions
2012-11-062.01AIKFixed bank 1 power options
2012-11-212.02AIKUpdated module diagram
2012-11-302.03AIKAdded Ethernet disable note
2012-12-192.04AIKFixed SPI Flash size on block diagram
2013-01-212.05AIKAdded PHY reset note
2013-03-132.06AIKConnectors current chapter moved to separate document
2013-03-132.07AIKChanged Bank 1 power supply description and VCCIO0 sources description
2016-01-29

2.08

AIK

Pause advertise correction
2016-11-05
Document ported to wiki and adapted to web presentation.

The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

I2C Interface

On-board I2C devices are connected to MIO48 and MIO49 which are configured as I2C1 by default. I2C addresses for on-board devices are listed in the table below:

...

PLL

...

JTAG Interface

JTAG access to the Xilinx Zynq-7000 is provided through B2B connector JM2. 

JTAG Signal

B2B Connector Pin

TCKJM2-99
TDIJM2-95
TDOJM2-97
TMSJM2-93 
Note
JTAGEN pin in B2B connector JM1 should be kept low or grounded for normal operation.

System Controller I/O Pins

Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

Pin NameModeFunctionDefault Configuration
EN1InputPower Enable

No hard wired function on PCB, when forced low pulls POR_B low to

emulate power on reset.

PGOODOutputPower GoodActive high when all on-module power supplies are working properly.
NOSEQ--No function.
RESINInputReset

Active low reset, gated to POR_B.

JTAGENInputJTAG SelectLow for normal operation.

Boot Mode Pin

By default the TE-0715 supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector.

MODE Signal State

Boot Mode

high or open

SD Card

low or ground

QSPI

LED's

LEDColorConnected toDescription and Notes

D2

Green

DONE

Reflects inverted DONE signal, ON when FPGA is not configured,

OFF as soon as PL is configured.

This LED will not operate if the SC can not power on the 3.3V output

rail that also powers the 3.3V circuitry on the module.

D3

Red

SC

System main status LED.

D4

Green

MIO7

User controlled, default OFF (when PS7 has not been booted).

Onboard Peripherals

Processing System (PS) Peripherals

...

Temperature compensated RTC.

...

Clocking

...

PS CLK

...

33.3333 Mhz

...

U11

...

PS_CLK

...

PS subsystem main clock.

...

ETH PHY reference

...

25 MHz

...

U9

...

-

...

USB PHY reference

...

52 MHz

...

U15

...

-

...

PLL reference

...

25 MHz

...

U18

...

-

...

GT REFCLK0

...

-

...

B2B

...

U9/V9

...

Externally supplied from baseboard.

...

GT REFCLK1

...

125 Mhz

...

U10 Si5338

...

U5/V5

...

Default clock is 125 MHz.

RTC - Real Time Clock

An temperature compensated Intersil ISL12020M is used for Real Time Clock (U16). Battery voltage must be supplied to the module from the main board. Battery backed registers can be accessed over I2C bus at slave address of 0x6F. General purpose RAM is at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device.

PLL - Phase-Locked Loop

There is a Silicon Labs I2C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I2C bus address 0x70.

PLL connection

...

IN1/IN2

...

Externally supplied

...

Needs decoupling on base board.

...

IN3

...

25MHz

...

Fixed input clock.

...

IN4

...

-

...

-

...

IN5/IN6

...

125MHz

...

Ethernet PHY output clock.

...

CLK0

...

-

...

Not used, disabled.

...

CLK1

...

-

...

Not used, disabled.

...

CLK2 A/B

...

125MHz

...

MGT reference clock 1.

...

CLK3A

...

125MHz

...

Bank 34 clock input.

...

CLK3B

...

-

...

Not used, disabled.

MAC-Address EEPROM

A Microchip 24AA025E48 EEPROM (U19) is used which contains a globally unique 48-bit node address, that is compatible with EUI-48(TM) and EUI-64(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C slave address 0x50.

Power and Power-On Sequence

Warning

TE0715-xx-30 has several HP banks on B2B connectors. Those banks have maximum voltage tolerance of 1.8V. Please check special instructions for the baseboard to be used with TE0715-xx-30.

Power Supply

Power supply with minimum current capability of 3A for system startup is recommended.

Power Consumption

Power Input PinMax Current
VINTBD*
3.3VINTBD*

 * TBD - To Be Determined soon with reference design setup.

Lowest power consumption is achieved when powering the module from single 3.3V supply. When using split 3.3V/5V supplies the power consumption (and heat dissipation) will rise, this is due to the DC/DC converter efficiency (it decreases when VIN/VOUT ratio rises). Typical power consumption is between 2-3W.

Power-On Sequence

For highest efficiency of on board DC/DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all baseboard I/O's are 3-stated at power-on until System Controller sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.

See Xilinx datasheet DS187 (for XC7Z015) or DS191 (for XC7Z030) for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0715 module.

Page break

Power Rails

...

Voltages on B2B-

Connectors

...

B2B JM1-Pin

...

B2B JM2-Pin

...

B2B JM3-Pin

...

Input/

Output

...

TE0715-xx-15: high range bank voltage,

...

TE0715-xx-15: high range bank voltage,

...

Bank Voltages

...

Bank          

...

Voltage

...

TE0715-xx-15        

...

TE0715-xx-30           

...

Technical Specifications

Recommended Operating Conditions

...

PL I/O bank supply voltage for HR

I/O banks (VCCO)

...

PL I/O bank supply voltage for HP

I/O banks (VCCO)

...

TE0715-xx-15 does not have

HP banks

...

Xilinx datasheet DS191

or DS187

...

TE0715-xx-15 does not have

HP banks

(*) Check datasheet

...

Absolute Maximum Ratings

...

Parameter

...

Units

...

Notes

...

VIN supply voltage

...

-0.3

...

6.0

...

V

...

3.3VIN supply voltage

...

-0.4

...

3.6

...

V

...

PL IO bank supply voltage for HP I/O banks (VCCO)

...

Voltage on module JTAG pins

...

-0.4

...

V

...

Storage temperature

...

-40

...

+85

...

°C

...

Note
Assembly variants for higher storage temperature range are available on request.
Note
Please check Xilinx datasheet DS187 (for XC7Z015) or DS191 (for XC7Z030) for complete list of absolute maximum and recommended operating ratings.

Physical Dimensions

  • Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers

  • Mating height with standard connectors: 8mm

  • PCB thickness: 1.6mm

  • Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers

 All dimensions are given in mm.

Image Removed   Image Removed

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Weight

26 g - Plain module

8.8 g - Set of bolts and nuts

Document Change History

...

Date

...

Revision

...

Contributors

...

Description

...

V38

 

...

Philipp Bernhardt, Antti Lukats, Thorsten Trenz,

Emmanuel Vassilakis, Jan Kumann

...

New overall document layout with shorter table of contents.

Revision 01 PCB pictures replaced with the revision 03 ones.

Fixed link to Master Pinout Table.

New default MIO mapping table design.

Revised Power-on section.

Added links to related Xilinx online documents.

Physical dimensions pictures revised.

Revision number picture with explanation added.

...

Philipp Bernhardt, Antti Lukats,

Thorsten Trenz, Emmanuel Vassilakis

...

Added the table "Recommended Operating Conditions"

Storage Temperature edited.

...

Philipp Bernhardt, Antti Lukats,

Thorsten Trenz

...

Hardware Revision History

...

Notes

...

01

...

Prototypes

...

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

...

Disclaimer

Include Page
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