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JTAGEN set carrier board CPLD into the chain for firmware update. In normal mode JTAG is routed directly to Module. Set S3-ENJTAG to off OFF to get access to carrier CPLD.
JTAGMODE set module CPLD into the chain for firmware update. In normal mode JTAG is routed directly to FPGA. Set S3-ENJTAG, S3-M1 and S3-M2 to on ON to get access to module CPLD. Attention VADJ is set to 1.8V in this mode.
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EN_FMC is set to logical one after delay.
VADJ Selection Table:
| M1 | M2 | Description |
|---|---|---|
| OFF | OFF | VADJ: 1.8V |
| OFF | ON | VADJ: 2.5V |
| ON | OFF | VADJ: 3.3V |
| ON | ON | VADJ: 1.8V, Attention: Also Module CPLD access is enabled, see JTAG description. |
Reset
RESIN (negative Reset) to module, can be set by S2 button.
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description |
|---|---|---|---|---|---|
| 2016-15-11 |
| REV02 | REV03, REV04 | John Hartfiel | Work in progress |
| 2016-15-11 | v.1820 | REV02 | REV03, REV04 | John Hartfiel | Revision 02 finished |
| 2016-04-11 |
v.1 | --- | John Hartfiel | Initial release | |
| All |
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