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EN_FMC is set to logical one after delay.
VADJ Selection Table:
| M1 | M2 | Description |
|---|---|---|
| OFF | OFF | VADJ: 1.8V |
| OFF | ON | VADJ: 2.5V |
| ON | OFF | VADJ: 3.3V |
| ON | ON | VADJ: 1.8V, Attention: Also Module CPLD access is enabled, see JTAG description. |
Reset
RESIN (negative Reset) to module, can be set by S2 button.
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description |
|---|---|---|---|---|---|
| 2016-15-11 |
| REV02 | REV03, REV04 | John Hartfiel | Work in progress |
| 2016-15-11 | v.20 | REV02 | REV03, REV04 | John Hartfiel | Revision 02 finished |
| 2016-04-11 |
v.1 | --- | John Hartfiel | Initial release | |
| All |
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