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Name	Direction	Pin	Description
ACBUS4	in	96
ACBUS5	in	88
ADBUS4	out	98
ADBUS7	out	97
BDBUS0	inout	87	Module UART0.RX << FTDI
BDBUS1	inout	86	Module UART0.TX >> FTDI
C_TCK	out	81
C_TDI	out	84
C_TDO	in	83
C_TMS	out	85
CM0	in	67	DIP Switch S3-M1
CM1	in	66	DIP Switch S3-M2
EN_FMC	out	35
EN1	out	53
JTAGEN	--	82	Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access) DIP Switch S3-JTAGEN
JTAGMODE	out	58	Enable JTAG access to CPLD for Firmware update on module CPLD (zero: JTAG routed to module FPGA, one: Module CPLD access) / currently_not_used (FPGA access only)
M_TCK	in	91
M_TDI	in	94
M_TDO	out	95
M_TMS	in	90
MIO10	inout	32	/ currently_not_used
MIO11	inout	31	/ currently_not_used
MIO12	inout	39	/ currently_not_used
MIO13	inout	34	/ currently_not_used
MIO14	inout	40	Module UART0.RX << BDBUS0
MIO15	inout	30	Module UART0.TX >> BDBUS1
MODE	out	28
NOSEQ	inout	29
PGOOD	inout	27
PHY_LED1	out	45
PHY_LED1_A	out	49
PHY_LED2	out	47
PHY_LED2_A	out	48
POK_FMC		36
RESIN	out	54
S1	in	75
S2	in	74
SD_DETECT	in	42
SD_WP	in	43
ULED1	out	78
ULED2	out	77
ULED3	out	76
ULED4	out	65
ULED5	out	71
ULED6	out	70
ULED7	out	69
ULED8	out	68
USB_OC	in	99
USR0		64
USR1		61
USR2		60
USR3		59
VID0	out	37
VID1	out	38
VID2	out	41
X6		19
Y0		15
Y1		14
Y2		13
Y3		10
Y4		9
Y5		8
Y6		7

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