Versions Compared

Old Version 14

changes.mady.by.user John Hartfiel

Saved on

compared with

New Version 15

changes.mady.by.user John Hartfiel

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

NameDirectionPinDescription
ACBUS4          in96FTDI / currently_not_used
ACBUS5          in88FTDI / currently_not_used
ADBUS4          out98FTDI  / get M_TCK
ADBUS7          out97FTDI / currently_not_used
BDBUS0          inout87FTDI / Module UART0.RX << FTDI
BDBUS1          inout86FTDI  /Module UART0.TX >> FTDI
C_TCKout81JTAG FTDI
C_TDIout84JTAG FTDI
C_TDOin83JTAG FTDI
C_TMSout85JTAG FTDI
CM0in67DIP Switch S3-M1
CM1in66DIP Switch S3-M2
EN_FMC          out35VADJ Power on
EN1             out53Power Enable Pin for Module CPLD
JTAGEN--82Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access)
DIP Switch S3-JTAGEN
JTAGMODEout58Enable JTAG access to CPLD for Firmware update on module CPLD (zero: JTAG routed to module FPGA, one: Module CPLD access)
M_TCK           in91JTAG Module
M_TDI           in94JTAG Module
M_TDO           out95JTAG Module
M_TMS           in90JTAG Module
MIO10           inout32  MIO / used by RGPIO Bus
MIO11           inout31MIO / used by RGPIO Bus
MIO12           inout39 MIO / used by RGPIO Bus
MIO13           inout34 MIO / used by RGPIO Bus
MIO14           inout40MIO / Module UART0.RX << BDBUS0
MIO15           inout30MIO / Module  UART0.TX >> BDBUS1
MODE            out28Boot Mode for Zynq Devices (Flash or SD)
NOSEQ           inout29/ currently_not_used
PGOOD           inout27/ currently_not_used
PHY_LED1        out45LED Ethernet
PHY_LED1_A      out49LED Ethernet / currently_not_used
PHY_LED2        out47LED Ethernet
PHY_LED2_A      out48LED  Ethernet / currently_not_used
POK_FMC          36LED  Ethernet / currently_not_used
RESIN           out54Module Reset
S1              in75User Button / used by RGPIO Bus
S2              in74User Button / Global Reset
SD_DETECT       in42SD Detection / used for FPGA Boot Mode
SD_WP           in43SD / RGPIO Bus
ULED1           out78LED D6
ULED2           out77LED D7
ULED3           out76LED D8
ULED4           out65LED D9
ULED5           out71LED D4
ULED6           out70LED D15
ULED7           out69LED D14
ULED8           out68LED D5
USB_OC          in99 
USR0in64DIP Switch S4-1 / used by RGPIO Bus (PCB REV04 only)
USR1in61DIP Switch S4-2 / used by RGPIO Bus (PCB REV04 only)
USR2in60DIP Switch S4-3 / used by RGPIO Bus (PCB REV04 only)
USR3in59DIP Switch S4-4 / used by RGPIO Bus (PCB REV04 only)
VID0            out37VADJ Voltage selection (EN5335QI)
VID1            out38VADJ Voltage selection (EN5335QI)
VID2            out41VADJ Voltage selection (EN5335QI)
X6              in19RGPIO Bus
Y0               15/ currently_not_used
Y1               14/ currently_not_used
Y2              in13RGPIO CLK
Y3              out10RGPIO TX
Y4              in9RGPIO RX
Y5               8/ currently_not_used
Y6              in7RGPIO Bus

...

Functional Description

JTAG

JTAGENB JTAGEN set carrier board CPLD into the Chain chain for Firmware firmware update. In normal mode every FMC JTAG will be set into the chain, when his FMCx_PRSNT is detected.

Power

Reset

Bootmode

RGPIO

...

JTAG is routed directly to Module. Set S3-ENJTAG to off to get access to carrier CPLD.

JTAGMODE set module CPLD into the chain for firmware update. In normal mode  JTAG is routed directly to FPGA. Set S3-ENJTAG, S3-M1 and S3-M2 to on to get access to module CPLD. Attention VADJ is set to 1.8V in this mode.

Power

EN1 is set to logical one after delay.

EN_FMC is set to logical one after delay.

Reset

RESIN (negative Reset) can be set by S2 Button.

Bootmode

Boot Mode is set to SD-Boot, when SD-Card is detected

RGPIO

RGPIO Master is a 32Bit Remote GPIO Interface to talk with FPGA over 3 lanes.

RGPIO Pin to FPGAValue
  
24-27reserved
28-31Interface detection
RGPIO Pin from FPGAValue
0-7LED 1-7
08-23unused
24-27reserved
28-31Interface detection

 

LED

UART

Appx. A: Change History and Legal Notices

...