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changes.mady.by.user Pedram Babakhani

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changes.mady.by.user John Hartfiel

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  • MPSoC:  XCZU2CG - Xilinx Zynq UltraScale+ MPSoC
    • Package: 1SBVA484E
    • Speed Grade: -1 (Slowest)

    • Temperature Grade: Expanded Extended (0 to +128 °C100 °C)

  • RAM/Storages:
    • SDRAM: LPDDR4 -3733 8Gb 256Mx16x 2 
    • SPI Flash 256Mb (32M x 8) 133 MHz
    • EEPROMs 2Kb (256 x 8)
    • EEPROMs 4Kb (512 x 8)

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Scroll Title
anchorTable_OV_BP
titleBoot Process

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OFF

MODE Signal State

MODE2

S9-C

MODE1

S9S1-B

MODE0

S9S1-A

Boot Mode

MODE[2:0]=000

OFFOFF

JTAG

MODE[2:0]=001

OFF

OFFONQSPI (24 bit)not supported

MODE[2:0]=010

OFFONOFFQSPI(32 bit)

MODE[2:0]=011

OFFONONSD0(2.0)
MODE[2:0]=111ONONONUSB(2.0)


Reset setting is available through Push Button BTN6.

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Scroll Title
anchorTable_SIP_B2B
titleGeneral I/O to Pin Header and Connectors Information

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12
FPGA BankConnector I/O Signal CountVoltage LevelNotes
Bank 503Micro USB, J8 (over FTDI)4 Single Ended3.3 VJTAG
Bank 500Micro USB, J8 (over FTDI)2 Single Ended3.3 VUART
Bank 500Micro SD Card, J97 Single Ended3.3 V
Bank 502Micro SD CardETH RJ45, J4 (over ETH PHY)14 Single Ended1.8 V
Bank 505, 502 USB 3.0, J11 (USB2 over USB PHY)2 Differential Pairs, 12 Single Ended-- / 1.8V0.85 V

Bank 505, 501

SSD M.2, U5

2 Differential Pairs

0.85 V

, 5 Single Ended

-- /

Bank 501SSD M.2, U55 Single Ended

3.3 V


Bank 505, 501Display Port Connector, J32 Differential Pairs0.85 VBank 26D-Sub Host Socket, J72 , 5 Single Ended--/ 3.3 V
Bank 26, 65, 66,D-Sub Host Socket (VGA), J714 Single Ended3.3 V / 1.8 V / 1.8 V
Bank 65Earphone, J123 Single Ended1.8 V
Bank 500Grove Connector, J102 Single Ended3.3 V
Bank 26Pmod Host Socket, J58 Single Ended3.3 V
Bank 26Pmod Host Socket, J6 8 Single Ended3.3 V


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Scroll Title
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titleTest Points Information

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Test Point

Signals

B2B Connector

Notes
1+1.1V_LPDDR4-
2+1.8V_MGTRAVTT-
3+1.8V_PL-
4FT_B_TX-
5DP_TX_PWR-
6GND-
7GND-
8PMIC2_SDA-
9PMIC2_TP-
10ONKEY2-
11PMIC2_SCL-
12DP_TX_HPD-
13DP_TX_PWR-
14INT_SCL1-
15INT_SDA1-
16FT_B_RX-
17CLOCKDIST_OE-
18+0.85V_VCCINT-
19+3.3V-
20+1.8V_PS-
21ERR_STATUS-
22+1.2V_PSPLL-
23GND-
24GND-
25PMIC1_SCA-
26PMIC1_SDA-
27ONKEY1-
28PMIC1_TP-
29POR_B-
30PSBATT-
31SRST_B-
32DONE-
33INIT_B-
34VBUS-
35USB_VBUS-
36PROG_B-
37ERR_OUT-


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

he TE0802 evaluation board has  one single QSPI flash connected as x4. Flash size depends on the assembly option, default 32MB

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titleQuad SPI Interface MIOs and Pins

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MIO PinSchematicU16 PinNotes
MIO0MIO0B2SPI_CLK
MIO1MIO1D2SPI_DQ1
MIO2MIO2C4SPI_DQ2
MIO3MIO3D4SPI_DQ3
MIO4MIO4D3SPI_DQ0
MIO5MIO5C2SPI_CS


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Scroll Title
anchorTable_OBP_I2C_FPGA_EEP
titleI2C Address for FPGA EEPROM

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MIO PinTypeI2C AddressDesignatorNotes
MIO8...94AA025E48T-I/OT0x50U2EEPROM with MAC



Scroll Title
anchorTable_OBP_FTDI_EEP
titleI2C FTDI EEPROM Interface Pins

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PinSchematicU18 PinNotes
CSEECS1FTDI
CLKEECLK2FTDI
DIN/DOEEDATA3/4FTDI


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