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Scroll Title |
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anchor | Figure_OV_BD |
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title | TE0802 Block Diagram |
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Scroll Ignore |
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draw.io Diagram |
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border | false |
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viewerToolbar | true |
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fitWindow | false |
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diagramDisplayName | |
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lbox | true |
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revision | 24 |
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diagramName | TE0802_OV_BD |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramWidth | 638 |
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Scroll Only |
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Bootmode signals must be set through DIP Switch S9S1.
Scroll Title |
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anchor | Table_OV_BP |
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title | Boot Process |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MODE Signal State | MODE1 S1-2(B) | MODE0 S1-1(A) | Boot Mode |
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MODE[2:0]=000 | OFF | OFF | JTAG | MODE[2:0]=001 | OFF | ON | not supported | MODE[2:0]=010 | ON | OFF | QSPI(32 bit) | MODE[2:0]=011 | ON | ON | SD0(2.0) |
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Scroll Title |
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anchor | Table_OBP |
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title | On-board Peripherals |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Quad SPI Flash Memory
Page properties |
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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Scroll Title |
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anchor | Table_OBP_DIP_SWITCH |
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title | DIP Switches |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Schematic | Connected to | Functionality | Note |
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S1AS1-1(A) | MODE0 | Pin J16, FPGA Bank 503 | DIP | Pulled-down to GND. | S1BS1-2(B) | MODE1 | Pin H15, FPGA Bank 503 | DIP | Pulled-down to GND. | S1CS1-3(C) | USER_CFG0 | Pin A4, FPGA Bank 66 | DIP | Pulled-down to GND. | S1DS1-4(D) | USER_CFG1 | Pin B4, FPGA Bank 66 | DIP | Pulled-down to GND. | S7AS7-1(A) | USER_SW7 | Pin M5, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. | S7BS7-2(B) | USER_SW6 | Pin M4, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. | S7CS7-3(C) | USER_SW5 | Pin J2, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. | S7DS7-4(D) | USER_SW4 | Pin K1, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. | S8AS8-1(A) | USER_SW3 | Pin L1, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. | S8BS8-2(B) | USER_SW2 | Pin M1, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. | S8CS8-3(C) | USER_SW1 | Pin P2, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. | S8DS8-4(D) | USER_SW0 | Pin P3, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. |
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Scroll Title |
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anchor | Table_RH_DCH |
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title | Document Change History |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Revision | Contributor | Description |
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Page info |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| Page info |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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showVersions | false |
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| Page info |
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infoType | Modified by |
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type | Flat |
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showVersions | false |
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| Technical Specifications updated | | 2020-11-19 | v.65 | Pedram Babakhani | | -- | all | Page info |
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infoType | Modified users |
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type | Flat |
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showVersions | false |
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