Page History

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Basic Notes
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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation

Overview

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General Design description
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ZynqMP PS Design with Linux Example and simple frequency counter to measure SI5338 Reference CLK with Vivado HW-Manager.

Key Features

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Revision History

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TE0820-test_board_noprebuilt-vivado_2018.2-build_03_20181031164506.zip

TE0820-test_board-vivado_2018.2-build_03_20181031164452.zip

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• new assembly variants
• update optional petalinux startup init script

...

• correction:
  • TE0820-03-4EV-1EA has 2GB DDR, now 2GB instead of 1GB is initialised
  • small changes on DDR setup of TE0820-02-2EG-1EE

...

• different design for REV03
• small petalinux changes
• IO renaming
• additional notes for FSBL generated with Win SDK
• changed *.bif

...

• bugfix board part files BANK1 MIO voltages
• Add "dummy" PS USB3 parameter so solve problems with some USB2 devices

...

TE0820-test_board-vivado_2017.4-build_10_20180524151356.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_10_20180524151342.zip

...

• solved Linux Flash issue
• new assembly variant

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• new assembly variants

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• solved JTAG/Linux issue

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• board part csv update

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• rework board part files
• solved  USB, QSPI and PHy issue

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Overview

ZynqMP PS Design with Linux Example and simple frequency counter to measure SI5338 Reference CLK with Vivado HW-Manager.
Wiki Resources page: http://trenz.org/te0820-info

Key Features

Revision History

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• solved SD SDX Cards Problem
• Separate csv name for all assembly variants

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• solved SD WP Problem

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• initial release

Release Notes and Know Issues

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Do not use HW Manager connection, or if debugging is nessecary:

1. Boot linux with usb terminal
2. From the terminal: root root mount ifconfig eth0
3. Open two new SSH terminals via ethernet: root root , run user application ...
4. Exit and close the usb terminal

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Requirements

Software

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Hardware

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Hardware Support
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Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

...

•  use slower DDR speed
• Xilinx has stopped ES1 support with 2018.2, please use 2017.4 reference design for ES1

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TE0820-02-2CG-1E

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Design supports following carriers:

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• Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers

...

• Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 cm carriers    
• Used as reference carrier.

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• Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers

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• Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers

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• Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers
• No SD Slot available, pins goes to Pin Header
• For TEBA0841 REV01, please contact TE support

Release Notes and Know Issues

Requirements

Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Design supports following carriers:

Additional HW Requirements:

Content

For general structure and of the reference design, see Project Delivery

Design Sources

Additional Sources

Prebuilt

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TE0820 "Test Board" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• Vivado/SDK/SDSoC
• Vivado Projects
• Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   Image Added
2. Press 0 and enter to start "Module Selection Guide"
3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
   
   1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
5. Create HDF and export to prebuilt folder
   
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
6. Create Linux (bl31.elf, uboot.elf and image.ub) with exported HDF
   
   1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
   2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
         Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
7. Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
   
   1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
8. Generate Programming Files with HSI/SDK
   
   1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
   2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

Launch

Programming

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Note: Depending on CPLD Firmware and Boot Mode settings, QSPI boot with Linux image on SD or complete SD Boot is possible.

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

1. Connect JTAG and power on carrier with module
2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
   Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
             optional "TE::pr_program_flash_binfile -swapp hello_te0820" possible
4. Copy image.ub on SD-Card
   • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
5. Insert SD-Card

SD

Use this description for CPLD Firmware with SD Boot selectable.

1. Copy image.ub and Boot.bin on SD-Card.
   • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
2. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)
3. Select SD Card or QSPI as Boot Mode (Depends on used programming variant)
   Note: See TRM of the Carrier, which is used.
4. Power On PCB
   Note: 1. ZynqMP Boot ROM loads PMU Firmware and  FSBL from SD/QSPI Flash into OCM, 2. FSBL loads ATF(bl31.elf) and U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

1. Open Serial Console (e.g. putty)
   
   1. Speed: 115200
   2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
2. Linux Console:
   Note: Wait until Linux boot finished For Linux Login use:
   
   1. User Name: root
   2. Password: root
3. You can use Linux shell now.
   1. I2C 0 Bus type: i2cdetect -y -r 0
   2. RTC check: dmesg | grep rtc
   3. ETH0 works with udhcpc
   4. USB type  "lsusb" or connect USB2.0 device
4. Option Features
   1. Webserver to get access to Zynq
      1. insert IP on web browser to start web interface
   2. init.sh scripts
      1. add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)
   
   

Vivado HW Manager

Additional HW Requirements:

...

Content

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For general structure and of the reference design, see Project Delivery

Design Sources

...

Additional Sources

...

Prebuilt

<!-- 

<table width="100%">
<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
</table>
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File

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File-Extension

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Description

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Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Add correct path:https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0803/Reference_Design/2017.1/Starterkit
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Reference Design is available on:

• TE0820 "Test Board" Reference Design

Design Flow

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Basic Design Steps
Add/ Remove project specific 
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Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• Vivado/SDK/SDSoC
• Vivado Projects
•  Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   Image Removed
2. Press 0 and enter for minimum setup
3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
4. Create Project
   
   1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
5. Create HDF and export to prebuilt folder
   
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
6. Create Linux (bl31.elf, uboot.elf and image.ub) with exported HDF
   
   1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
   2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
         Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
7. Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
   
   1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
8. Generate Programming Files with HSI/SDK
   
   1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
   2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

Launch

Programming

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Description of Block Design, Constrains...
BD Pictures from Export...
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Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Note: Depending on CPLD Firmware and Boot Mode settings, QSPI boot with Linux image on SD or complete SD Boot is possible.

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

1. Connect JTAG and power on carrier with module
2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
   Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
             optional "TE::pr_program_flash_binfile -swapp hello_te0820" possible
4. Copy image.ub on SD-Card
   • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
5. Insert SD-Card

SD

Use this description for CPLD Firmware with SD Boot selectable.

1. Copy image.ub and Boot.bin on SD-Card.
   • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
2. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)
3. Select SD Card or QSPI as Boot Mode (Depends on used programming variant)
   Note: See TRM of the Carrier, which is used.
4. Power On PCB
   Note: 1. ZynqMP Boot ROM loads PMU Firmware and  FSBL from SD/QSPI Flash into OCM, 2. FSBL loads ATF(bl31.elf) and U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

1. Open Serial Console (e.g. putty)
   
   1. Speed: 115200
   2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
2. Linux Console:
   Note: Wait until Linux boot finished For Linux Login use:
   
   1. User Name: root
   2. Password: root
3. You can use Linux shell now.
   1. I2C 0 Bus type: i2cdetect -y -r 0
   2. RTC check: dmesg | grep rtc
   3. ETH0 works with udhcpc
   4. USB type  "lsusb" or connect USB2.0 device
      

...

SI5338_CLK0 Counter: 

1. Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
   1. Set radix from VIO signals to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz
      

...

• User LED, see: TE0820 CPLD#LED

Scroll Title
anchor Figure_VHM title Vivado Hardware Manager
Image Modified

PCB REV01, REV02 Design:

• PHY LEDS, see: TE0820-REV01_REV02 CPLD#X0/X1Pin
• CPLD Firmware, see: TE0820-REV01_REV02 CPLD#X0/X1Pin

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Scroll Title
anchor Figure_VHM1 title Vivado Hardware Manager PCB REV01,REV02
Image Modified

System Design - Vivado

Block Design

PCB REV03

PCB REV01 REV02

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Software Design - SDK/HSI

For SDK project creation, follow instructions from:

...

zynqmp_fsbl

TE modified 2018.2 3 FSBL

ChangesGeneral:

• Si5338 Configuration, ETH+OTG Reset over GPIOsee xfsbl_boardModified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h, xfsbl_main/.c(search for 'TE Mod' on source code)
• Add register_mapFiles:  te_xfsbl_hooks.h, si5338.c, si5338.h

...

• /.c (for hooks and board)\n\
• General Changes: 
  
  • Display FSBL Banner and Device Name

Module Specific:

• Add Files: all TE Files start with te_*
  
  • Si5338 Configuration
  • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2018.2 3 FSBL

Changes:

General:

• Modified Files: xfsbl
• Set FSBL Boot Mode to JTAG
• Disable Memory initialisation
• see  xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c

...

• General Changes:
  
  •  Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

...

Software Design -  PetaLinux

For PetaLinux installation and  project creation, follow instructions from:

• PetaLinux KICKstart

Config

Activate:

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

• CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y

U-Boot-Boot

Start with petalinux-config -c u-boot
Changes:

• CONFIG_ENV_IS_NOWHERE=y

• CONFIG_ENV_IS_IN_SPI_FLASH is not set

Change platform-top.h:

#include <configs/platform-auto.h>
#define CONFIG_SYS_BOOTM_LEN 0xF000000

#define DFU_ALT_INFO_RAM \
                "dfu_ram_info=" \
        "setenv dfu_alt_info " \
        "image.ub ram $netstart 0x1e00000\0"h>
#define CONFIG_SYS_BOOTM_LEN 0xF000000

#define DFU_ALT_INFO_RAM \
        "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
        "thor_ram=run dfu_ram_info && thordown 0 ram 0\0"

#define DFU_ALT_INFO_MMC =" \
        "setenv dfu_mmcalt_info= " \
        "set dfu_alt_info image.ub ram $netstart 0x1e00000\0" \
        "${kernel_image} fatdfu_ram=run dfu_ram_info && dfu 0 1\\\\;ram 0\0" \
        "dfuthor_mmcram=run dfu_mmcram_info && dfuthordown 0 mmcram 0\0"

#define DFU_ALT_INFO_MMC \
        "thordfu_mmc=run_info=" \
        "set dfu_mmcalt_info &&" thordown\
 0 mmc 0\0"

/*Required for uartless designs */
#ifndef CONFIG_BAUDRATE
#define CONFIG_BAUDRATE 115200
#ifdef CONFIG_DEBUG_UART
#undef CONFIG_DEBUG_UART
#endif
#endif

/*Define CONFIG_ZYNQMP_EEPROM here and its necessaries in u-boot menuconfig if you had EEPROM memory. */
#ifdef CONFIG_ZYNQMP_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
#define CONFIG_CMD_EEPROM
#define CONFIG_ZYNQ_EEPROM_BUS          5
#define CONFIG_ZYNQ_GEM_EEPROM_ADDR     0x54
#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET  0x20
#endif

Device Tree

/include/ "system-conf.dtsi"
/ {
};


/* SDIO */

&sdhci1 {
   disable-wp;
   no-1-8-v;
};

/* ETH PHY */
&gem3 {

    status = "okay";
  ethernet_phy0: ethernet-phy@0 {
 "${kernel_image} fat 0 1\\\\;" \
        "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \
        "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0"

/*Required for uartless designs */
#ifndef CONFIG_BAUDRATE
#define CONFIG_BAUDRATE 115200
#ifdef CONFIG_DEBUG_UART
#undef CONFIG_DEBUG_UART
#endif
#endif

/*Define CONFIG_ZYNQMP_EEPROM here and its necessaries in u-boot menuconfig if you had EEPROM memory. */
#define CONFIG_ZYNQMP_EEPROM
#ifdef CONFIG_ZYNQMP_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
#define CONFIG_CMD_EEPROM
#define CONFIG_ZYNQ_EEPROM_BUS        compatible = "marvell,88e1510";
  0
#define CONFIG_ZYNQ_GEM_EEPROM_ADDR     0x50
#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET  0xFA
#endif

Device Tree

/include/ "system-conf.dtsi"
/ {
};


/* SDIO */

&sdhci1 {
   disable-wp;
   no-1-8-v device_type = "ethernet-phy";
            reg = <1>;
    };
};

/* USBETH 2.0PHY */

&dwc3_0gem3 {

    status = "okay";
  ethernet_phy0:  dr_modeethernet-phy@0 {
        compatible = "hostmarvell,88e1510";
    maximum-speed    device_type = "highethernet-speedphy";
         /delete-property/phy-names;
   reg  /delete-property/phys= <1>;
    /delete-property/snps,usb3_lpm_capable};
};

/* QSPIUSB PHY2.0 */

&qspidwc3_0 {
    #address-cellsstatus = <1>"okay";
    #size-cellsdr_mode = <0>"host";
    statusmaximum-speed = "okayhigh-speed";
    flash0: flash@0 {
        compatible = "jedec,spi-nor"/delete-property/phy-names;
    /delete-property/phys;
    reg = <0x0>;
    /delete-property/snps,usb3_lpm_capable;
};

/* QSPI PHY */
&qspi {
    #address-cells = <1>;
        #size-cells = <1><0>;
    };
};

/* DMA not used: Reduce error messages on linux.*/

&lpd_dma_chan1 {
 status = "okay";
    flash0: flash@0 {
        statuscompatible = "disabledjedec,spi-nor";
};
&lpd_dma_chan2 {
        statusreg = "disabled";
};
&lpd_dma_chan3 {
<0x0>;
        status#address-cells = "disabled"<1>;
};
&lpd_dma_chan4 {
    status = "disabled";
};
&lpd_dma_chan5 {
    status = "disabled";
};
&lpd_dma_chan6 {
    status = "disabled";
};
&lpd_dma_chan7 {
    status = "disabled";
};
&lpd_dma_chan8 {
    status = "disabled";
};

Kernel

Deactivate:

• CONFIG_CPU_IDLE        (only needed to fix JTAG Debug issue)

• CONFIG_CPU_FREQ      (only needed to fix JTAG Debug issue)

Rootfs

Activate:

• i2c-tools

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

Additional Software

<!--
Add Description for other Software, for example SI CLK Builder ...
 -->

SI5338

Download  ClockBuilder Desktop for SI5338

1. Install and start ClockBuilder
2. Select SI5338
3. Options → Open register map file
   Note: File location <design name>/misc/Si5338/RegisterMap.txt
4. Modify settings
5. Options → save C code header files
6. Replace Header files from FSBL template with generated file

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

 #size-cells = <1>;
    };
};

Kernel

Start with petalinux-config -c kernel

Changes:

• CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)

• CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)

• CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set (only needed to fix JTAG Debug issue)
• CONFIG_EDAC_CORTEX_ARM64=y

Rootfs

Start with petalinux-config -c rootfs

Changes:

• CONFIG_i2c-tools=y
• CONFIG_busybox-httpd=y (for web server app)

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

webfwu

Webserver application accemble for Zynq access. Need busybox-httpd

Additional Software

SI5338

File location <design name>/misc/Si5338/Si5338-*.slabtimeproj

General documentation how you work with these project will be available on Si5338

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

v.9

Legal Notices

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