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Overview


ZynqMP PS Design with Linux Example and simple frequency counter to measure SI5338 Reference CLK with Vivado HW-Manager.
Wiki Resources page: http://trenz.org/te0820-info

Key Features

  • Vitis/Vivado 2020.2
  • PetaLinux
  • SD
  • ETH
  • USB
  • I2C
  • RTC
  • FMeter
  • MAC from EEPROM
  • User LED (PCB REV03 only)
  • Modified FSBL for SI5338 programming
  • Special FSBL for QSPI programming

Revision History

DateVivadoProject BuiltAuthorsDescription
2020-06-012020.2TE0820-test_board-vivado_2020.2-build_5_20210601084124.zip
TE0820-test_board_noprebuilt-vivado_2020.2-build_5_20210601092528.zip
John Hartfiel
  • 2020.2 release
  • new assembly variants
2020-04-082019.2TE0820-test_board_noprebuilt-vivado_2019.2-build_10_20200408073458.zip
TE0820-test_board-vivado_2019.2-build_10_20200408073444.zip
John Hartfiel
  • script update
  • new assembly variants
2020-03-252019.2TE0820-test_board_noprebuilt-vivado_2019.2-build_8_20200325083817.zip
TE0820-test_board-vivado_2019.2-build_8_20200325083750.zip
John Hartfiel
  • script update
  • Board Part update (minor changes)
2020-01-222019.2TE0820-test_board_noprebuilt-vivado_2019.2-build_3_20200122154341.zip
TE0820-test_board-vivado_2019.2-build_3_20200122154318.zip
John Hartfiel
  • script update for linux user
2020-01-142019.2TE0820-test_board-vivado_2019.2-build_3_20200114081551.zip
TE0820-test_board_noprebuilt-vivado_2019.2-build_3_20200114081612.zip
John Hartfiel
  • add fsbl_flash binary
  • Vitis script updates (include linux domain and prebuilt linux files for vitis)
  • prebuilt binary export on selection guide
2019-12-192019.2TE0820-test_board-vivado_2019.2-build_1_20191219075647.zip
TE0820-test_board_noprebuilt-vivado_2019.2-build_1_20191219080228.zip
John Hartfiel
  • 2019.2 update
  • Vitis support
2019-10-292018.3TE0820-test_board_noprebuilt-vivado_2018.3-build_09_20191029071045.zip
TE0820-test_board-vivado_2018.3-build_09_20191029071028.zip
John Hartfiel
  • new assembly variants
2019-08-092018.3TE0820-test_board_noprebuilt-vivado_2018.3-build_07_20190809084040.zip
TE0820-test_board-vivado_2018.3-build_07_20190809083901.zip
John Hartfiel
  • bugfix fsbl (removed second PSU init)
2019-06-192018.3TE0820-test_board_noprebuilt-vivado_2018.3-build_06_20190619073300.zip
TE0820-test_board-vivado_2018.3-build_06_20190619073243.zip
John Hartfiel
  • new assembly variants
  • USB2 only (change PS IP and device tree)
  • FSBL changes
2019-04-012018.3TE0820-test_board_noprebuilt-vivado_2018.3-build_03_20190401130135.zip
TE0820-test_board-vivado_2018.3-build_03_20190401130123.zip
John Hartfiel
  • renamed ...D variants to ...A
2019-02-212018.3

TE0820-test_board_noprebuilt-vivado_2018.3-build_01_20190221103025.zip
TE0820-test_board-vivado_2018.3-build_01_20190221102913.zip

John Hartfiel
  • TE Script update
  • rework of the FSBLs
  • SI5338 CLKBuilder Pro Project
  • some additional Linux features
  • MAC from EEPROM
  • new assembly variants
  • remove special compiler flags, which was needed in 2018.2
2018-10-312018.2

TE0820-test_board_noprebuilt-vivado_2018.2-build_03_20181031164506.zip

TE0820-test_board-vivado_2018.2-build_03_20181031164452.zip

John Hartfiel
  • new assembly variants
  • update optional petalinux startup init script
2018-09-122018.2TE0820-test_board_noprebuilt-vivado_2018.2-build_03_20180912094615.zip
TE0820-test_board-vivado_2018.2-build_03_20180912094558.zip
John Hartfiel
  • correction:
    • TE0820-03-4EV-1EA has 2GB DDR, now 2GB instead of 1GB is initialised
    • small changes on DDR setup of TE0820-02-2EG-1EE
2018-08-152018.2TE0820-test_board-vivado_2018.2-build_01_20180706212937.zip
TE0820-test_board_noprebuilt-vivado_2018.2-build_01_20180706212952.zip
John Hartfiel
  • different design for REV03
  • small petalinux changes
  • IO renaming
  • additional notes for FSBL generated with Win SDK
  • changed *.bif
2018-06-192017.4TE0820-test_board-vivado_2017.4-build_10_20180619160713.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_10_20180619160728.zip
John Hartfiel
  • bugfix board part files BANK1 MIO voltages
  • Add "dummy" PS USB3 parameter so solve problems with some USB2 devices
2018-05-242017.4

TE0820-test_board-vivado_2017.4-build_10_20180524151356.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_10_20180524151342.zip

John Hartfiel
  • solved Linux Flash issue
  • new assembly variant
2018-04-252017.4TE0820-test_board-vivado_2017.4-build_07_20180425134435.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_07_20180425134459.zip
John Hartfiel
  • new assembly variants
2018-02-062017.4TE0820-test_board-vivado_2017.4-build_06_20180206203359.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_06_20180206203414.zip
John Hartfiel
  • solved JTAG/Linux issue
2018-02-012017.4TE0820-test_board-vivado_2017.4-build_05_20180201084319.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_05_20180201094724.zip
John Hartfiel
  • board part csv update
2018-01-242017.4TE0820-test_board-vivado_2017.4-build_05_20180124085247.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_05_20180124085303.zip
John Hartfiel
  • rework board part files
  • solved USB, QSPI and PHY issue
2017-11-212017.2TE0820-test_board-vivado_2017.2-build_05_20171121160552.zip
TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171121160606.zip
John Hartfiel
  • solved SD SDX Cards Problem
  • Separate csv name for all assembly variants
2017-11-202017.2TE0820-test_board-vivado_2017.2-build_05_20171120162931.zip
TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171120162851.zip
John Hartfiel
  • solved SD WP Problem
2017-10-192017.2TE0820-test_board-vivado_2017.2-build_05_20171019104824.zip
TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171019104837.zip
John Hartfiel
  • initial release
Design Revision History

Release Notes and Know Issues

IssuesDescriptionWorkaroundTo be fixed version
Flash access on LinuxDevice tree is not correct on Linuxadd compatibility to "compatible “jedec,spi-nor”"Solved with 20180524 update
USB UART Terminal is blocked / SDK Debugging is blockedThis happens only with 2017.4 Linux , when JTAG connection is established on Vivado HW Manager.

Do not use HW Manager connection, or if debugging is necessary:

  1. Boot linux with usb terminal
  2. From the terminal: root root mount ifconfig eth0
  3. Open two new SSH terminals via ethernet: root root , run user application ...
  4. Exit and close the usb terminal
Solved with 20180206 update
Known Issues

Requirements

Software

SoftwareVersionNote
Vitis2020.2needed, Vivado is included into Vitis installation
PetaLinux2020.2needed
SI ClockBuilder Pro---optional
Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0820-ES1           es1            REV01     1GB      64MB      4GB        NA                     Not longer supported by vivado   
TE0820-02-02EG-1E2eg_1e_1gbREV021GB64MB4GBNA NA 
TE0820-02-02EG-1E32eg_1e_1gbREV021GB64MB4GB2.5 mm connectorsNA 
TE0820-02-02CG-1E2cg_1e_1gbREV021GB64MB4GBNA NA 
TE0820-02-03EG-1E3eg_1e_1gbREV021GB64MB4GBNA NA 
TE0820-02-03EG-1E33eg_1e_1gbREV021GB64MB4GB2.5 mm connectorsNA 
TE0820-02-03CG-1E3cg_1e_1gbREV021GB64MB4GBNA NA 
TE0820-02-02EG-1EA2eg_1e_1gbREV021GB128MB4GBNA NA 
TE0820-02-02EG-1EL2eg_1e_1gbREV021GB128MB4GB2.5 mm connectorsNA 
TE0820-02-02CG-1EA2cg_1e_1gbREV021GB128MB4GBNA NA 
TE0820-02-03EG-1EA3eg_1e_1gbREV021GB128MB4GBNA NA 
TE0820-02-03EG-1EL3eg_1e_1gbREV021GB128MB4GB2.5 mm connectorsNA 
TE0820-02-03CG-1EA3cg_1e_1gbREV021GB128MB4GBNA NA 
TE0820-02-04CG-1EA4cg_1e_1gbREV021GB128MB4GBNA NA 
TE0820-03-04EV-1EA4ev_1e_2gbREV032GB128MB4GBNA NA 
TE0820-03-02CG-1EA2cg_1e_2gbREV032GB128MB4GBNA NA 
TE0820-03-02EG-1EA2eg_1e_2gbREV032GB128MB4GBNA NA 
TE0820-03-02EG-1EL2eg_1e_2gbREV032GB128MB4GB2.5 mm connectorsNA 
TE0820-03-03CG-1EA3cg_1e_2gbREV032GB128MB4GBNA NA 
TE0820-03-04CG-1EA4cg_1e_2gbREV032GB128MB4GBNA NA 
TE0820-03-03EG-1EA3eg_1e_2gbREV032GB128MB4GBNA NA 
TE0820-03-03EG-1EL3eg_1e_2gbREV032GB128MB4GB2.5 mm connectorsNA 
TE0820-03-2AI21FA2cg_1i_2gbREV032GB128MB8GBNA NA 
TE0820-03-2BE21FL2eg_1e_2gbREV032GB128MB8GB2.5 mm connectorsNA 
TE0820-03-3AI210A3cg_1i_2gbREV032GB128MB0GBNA NA 
TE0820-03-3BE21FA3eg_1e_2gbREV032GB128MB8GBNA NA 
TE0820-03-3BE21FL3eg_1e_2gbREV032GB128MB8GB2.5 mm connectorsNA 
TE0820-03-02CG-1ED2cg_1e_2gbREV032GB128MB8GBNA NA 
TE0820-03-2AE21FA2cg_1e_2gbREV032GB128MB8GBNA NA 
TE0820-03-2BE21FA2eg_1e_2gbREV032GB128MB8GBNA NA 
TE0820-03-3AE21FA3cg_1e_2gbREV032GB128MB8GBNA NA 
TE0820-03-3AI21FA3cg_1i_2gbREV032GB128MB8GBNA NA 
TE0820-03-4AE21FA4cg_1e_2gbREV032GB128MB8GBNA NA 
TE0820-03-4DE21FA4ev_1e_2gbREV032GB128MB8GBNA NA 
TE0820-03-4DI21FA4ev_1i_2gbREV032GB128MB8GBNA NA 
TE0820-03-4DE21FL4ev_1e_2gbREV032GB128MB8GB2.5 mm connectorsNA 
TE0820-03-4AE21FI4cg_1e_x_2gbREV032GB128MB8GBwithout ETH PHYNA 
TE0820-03-4DE21FC4ev_1e_2gbREV032GB128MB8GBwithout encryption NCNRNA 
TE0820-03-4AI21FI4cg_1i_x_2gbREV032GB128MB8GBwithout ETH PHYNA 
TE0820-03-5DR21FA5ev_1q_2gbREV032GB128MB8GBNA NA 
TE0820-03-2BI21FA2eg_1i_2gbREV032GB128MB8GBNA NA 
TE0820-03-2BI21FL2eg_1i_2gbREV032GB128MB8GB2.5 mm connectorsNA 
TE0820-03-5DI21FA5ev_1i_2gbREV032GB128MB8GBNA NA 
TE0820-04-2AE21FA2cg_1e_2gbREV042GB128MB8GBNA NA 
TE0820-04-2AI21FA2cg_1i_2gbREV042GB128MB8GBNA NA 
TE0820-04-2BE21FA2eg_1e_2gbREV042GB128MB8GBNA NA 
TE0820-04-2BE21FAJ2eg_1e_2gbREV042GB128MB8GBwithout spacersNA 
TE0820-04-2BE21FL*2eg_1e_2gbREV042GB128MB8GB2.5 mm connectorsNA 
TE0820-04-2BE21-V12eg_1e_2gbREV042GB128MB8GBNA Customised
TE0820-04-2BI21FA2eg_1i_2gbREV042GB128MB8GBNA NA 
TE0820-04-2BI21FL2eg_1i_2gbREV042GB128MB8GB2.5 mm connectorsNA 
TE0820-04-3AE21FA3cg_1e_2gbREV042GB128MB8GBNA NA 
TE0820-04-3AI21FA3cg_1i_2gbREV042GB128MB8GBNA NA 
TE0820-04-3AI21FAT3cg_1i_2gbREV042GB128MB8GBNA Customer supplied
TE0820-04-3BE21FA3eg_1e_2gbREV042GB128MB8GBNA NA 
TE0820-04-3BE21FL3eg_1e_2gbREV042GB128MB8GB2.5 mm connectorsNA 
TE0820-04-3BE21KA3eg_1e_2gbREV042GB128MB64GBNA NA 
TE0820-04-4AE21FA4cg_1e_2gbREV042GB128MB8GBNA NA 
TE0820-04-4AI21FI4cg_1i_x_2gbREV042GB128MB8GBwithout ETH PHYNA 
TE0820-04-4BI21KL4eg_1i_2gbREV042GB128MB64GB2.5 mm connectorsNA 
TE0820-04-4DE21FA4ev_1e_2gbREV042GB128MB8GBNA NA 
TE0820-04-4DE21FL4ev_1e_2gbREV042GB128MB8GB2.5 mm connectorsNA 
TE0820-04-4DI21FA4ev_1i_2gbREV042GB128MB8GBNA NA 
TE0820-04-5DI21FA5ev_1i_2gbREV042GB128MB8GBNA NA 
TE0820-04-5DR21FA5ev_1q_2gbREV042GB128MB8GBNA NA 

*used as reference

Hardware Modules

Design supports following carriers:

Carrier ModelNotes
TE0701
TE0703*
TE0705
TE0706
TEBA0841
  • Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers
  • No SD Slot available, pins goes to Pin Header
  • For TEBA0841 REV01, please contact TE support

*used as reference

Hardware Carrier

Additional HW Requirements:

Additional HardwareNotes
USB Cable for JTAG/UARTCheck Carrier Board and Programmer for correct typ
XMOD ProgrammerCarrier Board dependent, only if carrier has no own FTDI
CoolerIt's recommended to use cooler on ZynqMP device
Additional Hardware

Content

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

TypeLocationNotes
Vivado<project folder>\block_design
<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files
Vivado Project will be generated by TE Scripts
Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<project folder>\os\petalinuxPetaLinux template with current configuration
Design sources

Additional Sources

TypeLocationNotes
SI5338<project folder>\misc\Si5338SI5338 Project with current PLL Configuration
init.sh<project folder>\sd\Additional Initialization Script for Linux
Additional design sources

Prebuilt


File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
Boot Source*.scr

Distro Boot file

DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems
Prebuilt files (only on ZIP with prebuilt content)

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Design Flow


Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

    _create_win_setup.cmd/_create_linux_setup.sh
    ------------------------Set design paths----------------------------
    -- Run Design with: _create_win_setup
    -- Use Design Path: <absolute project path>
    --------------------------------------------------------------------
    -------------------------TE Reference Design---------------------------
    --------------------------------------------------------------------
    -- (0)  Module selection guide, project creation...prebuilt export...
    -- (1)  Create minimum setup of CMD-Files and exit Batch
    -- (2)  Create maximum setup of CMD-Files and exit Batch
    -- (3)  (internal only) Dev
    -- (4)  (internal only) Prod
    -- (c)  Go to CMD-File Generation (Manual setup)
    -- (d)  Go to Documentation (Web Documentation)
    -- (g)  Install Board Files from Xilinx Board Store (beta)
    -- (a)  Start design with unsupported Vivado Version (beta)
    -- (x)  Exit Batch (nothing is done!)
    ----
    Select (ex.:'0' for module selection guide):
  2. Press 0 and enter to start "Module Selection Guide"
  3. Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
    • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

      Note: Select correct one, see also Vivado Board Part Flow

  4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

    run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
    TE::hw_build_design -export_prebuilt

    Using Vivado GUI is the same, except file export to prebuilt folder.

  5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
    • use TE Template from "<project folder>\os\petalinux"
    • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

  6. Configure the boot.scr file as needed, see Distro Boot with Boot.scr
  7. Copy PetaLinux build image files to prebuilt folder
    • copy u-boot.elf, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"


  8. Generate Programming Files with Vitis

    run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
    TE::sw_run_vitis -all
    TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

    TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

Launch


Programming

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Note: Depending on CPLD Firmware and Boot Mode settings, QSPI boot with Linux image on SD or complete SD Boot is possible.

Get prebuilt boot binaries

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select create and open delivery binary folder

      Note: Folder "<project folder>/_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

QSPI-Boot mode

Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

    run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
    TE::pr_program_flash -swapp u-boot
    TE::pr_program_flash -swapp hello_te0820 (optional)

    To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup

  3. Copy image.ub and boot.scr on SD or USB
    • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
  4. Set Boot Mode to QSPI-Boot and insert SD or USB.
    • Depends on Carrier, see carrier TRM.

SD-Boot mode

  1. Copy image.ub, boot.src and Boot.bin on SD
    • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
    • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.

JTAG

Not used on this example.

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

    Note: See TRM of the Carrier, which is used.

    Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
    The boot options described above describe the common boot processes for this hardware; other boot options are possible.
    For more information see Distro Boot with Boot.scr

  4. Power On PCB

    1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

Linux

  1. Open Serial Console (e.g. putty)
    • Speed: 115200
    • select COM Port

      Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

  2. Linux Console:

    petalinux login: root
    Password: root

    Note: Wait until Linux boot finished

  3. You can use Linux shell now.

    i2cdetect -y -r 0	(check I2C 0 Bus)
    dmesg | grep rtc	(RTC check)
    udhcpc				(ETH0 check)
    lsusb				(USB check)
  4. Option Features

    • Webserver to get access to Zynq
      • insert IP on web browser to start web interface
    • init.sh scripts
      • add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")


Vivado HW Manager

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)

  • Control:
    • User LED (PCB REV03 and newer)
  • Monitoring:
    • SI5338_CLK0 Counter: 
      • Set radix from VIO signals to unsigned integer.
        Note: Frequency Counter is inaccurate and displayed unit is Hz
      • SI5338 CLK is configured to 200MHz by default.


PCB REV03 Design:

Vivado Hardware Manager

PCB REV01, REV02 Design:

Vivado Hardware Manager PCB REV01,REV02

System Design - Vivado


Block Design

PCB REV03

Block Design PCB REV03

PCB REV01 REV02

Block Design PCB REV01 REV02


PS Interfaces

Activated interfaces:

TypeNote
DDR
QSPIMIO
SD0MIO
SD1MIO
I2C0MIO
UART0MIO
GPIO0MIO
SWDT0..1
TTC0..3
GEM3MIO
USB0MIO, USB2 only


Constrains

Basic module constrains

_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design

Design specific constrain

_i_io.xdc
set_property PACKAGE_PIN K9 [get_ports {SI5338_CLK0_D_clk_p[0]}]
set_property IOSTANDARD LVDS [get_ports {SI5338_CLK0_D_clk_p[0]}]
set_property DIFF_TERM TRUE [get_ports {SI5338_CLK0_D_clk_p[0]}]

set_property PACKAGE_PIN H1 [get_ports {x0[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {x0[0]}]
set_property PACKAGE_PIN J1 [get_ports {x1[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {x1[0]}]

Software Design - Vitis


For Vitis project creation, follow instructions from:

Vitis

Application

Template location: "<project folder>\sw_lib\sw_apps\"

zynqmp_fsbl

TE modified 2020.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2020.2 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    • Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design - PetaLinux


For PetaLinux installation and project creation, follow instructions from:

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

  • CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
  • CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""

U-Boot

Start with petalinux-config -c u-boot
Changes:

  • CONFIG_I2C_EEPROM=y
  • CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
  • CONFIG_SYS_I2C_EEPROM_ADDR=0x50
  • CONFIG_SYS_I2C_EEPROM_BUS=0
  • CONFIG_SYS_EEPROM_SIZE=256
  • CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0
  • CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0
  • CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1
  • CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0
  • CONFIG_SD_BOOT=y

Change platform-top.h:

 

Device Tree

/include/ "system-conf.dtsi"
/ {
  chosen {
    xlnx,eeprom = &eeprom;
  };
};
/*emmc*/
&sdhci0 {
    // disable-wp;
    no-1-8-v;
 
};
/* SDIO */
&sdhci1 {
   disable-wp;
   no-1-8-v;
};
 
/* ETH PHY */
&gem3 {
 
    status = "okay";
  ethernet_phy0: ethernet-phy@0 {
        compatible = "marvell,88e1510";
        device_type = "ethernet-phy";
            reg = <1>;
    };
};
/* USB 2.0 */
  
/* USB  */
&dwc3_0 {
    status = "okay";
    dr_mode = "host";
    maximum-speed = "high-speed";
    /delete-property/phy-names;
    /delete-property/phys;
    /delete-property/snps,usb3_lpm_capable;
     snps,dis_u2_susphy_quirk;
    snps,dis_u3_susphy_quirk;
};
    
&usb0 {
    status = "okay";
    /delete-property/ clocks;
    /delete-property/ clock-names;
    clocks = <0x3 0x20>;
    clock-names = "bus_clk";
};
 
 
 
 
/* QSPI PHY */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};
 
&i2c0 {
  eeprom: eeprom@50 {
     compatible = "atmel,24c08";
     reg = <0x50>;
  };
};
   

Kernel

Start with petalinux-config -c kernel

Changes:

  • CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)

  • CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)

  • CONFIG_EDAC_CORTEX_ARM64=y

Rootfs

Start with petalinux-config -c rootfs

Changes:

  • CONFIG_i2c-tools=y
  • CONFIG_busybox-httpd=y (for web server app)
  • CONFIG_packagegroup-petalinux-utils(util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)

Applications

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"

startup

Script App to load init.sh from SD Card if available.

webfwu

Webserver application suitable for Zynq access. Need busybox-httpd

Additional Software



SI5338

File location "<project folder>\misc\Si5338\Si5338-*.slabtimeproj"

General documentation how you work with these project will be available on Si5338

Appx. A: Change History and Legal Notices


Document Change History

To get content of older revision got to "Change History" of this page and select older document revision number.

DateDocument RevisionAuthorsDescription

  • document style update
2021-06-01v.64John Hartfiel
  • 2020.2 update
  • new assembly variants
  • document style update
2020-05-07v.62John Hartfiel
  • update programming section
2020-04-08v.61John Hartfiel
  • script update
  • new assembly variants
2020-03-25v.60John Hartfiel
  • script update
2020-01-21v.59John Hartfiel
  • Script update for linux user
2020-01-14v.58John Hartfiel
  • Script update, new features
  • doc update
  • add missing binary files
2019-12-19v.57John Hartfiel
  • 2019.2 release
2019-10-29v.56John Hartfiel
  • new assembly variants
2019-08-09v.55John Hartfiel
  • bugfix fsbl
2019-06-19v.54John Hartfiel
  • design changes
  • new variants
2019-04-01v.53John Hartfiel
  • some notes
  • renamed ..D variants to ...A

2018-09-21

v.47John Hartfiel
  • 2018.3 release finished (include design reworks)

2018-10-31

v.43John Hartfiel
  • Update Design files for 2GB variants
  • rebuilt petalinux for optional init script

2018-09-12

v.41John Hartfiel
  • Update Design files for 2GB variants

2018-07-11

v.40John Hartfiel
  • add notes to ES1

2018-07-06

v.38John Hartfiel
  • 2018.2 release finished

2018-06-19

v.34John Hartfiel
  • Design Files Update

2018-02-13

v.29John Hartfiel
  • Design Files Update
2018-02-06v.27John Hartfiel
  • Design Files Update
2018-01-29v.26John Hartfiel
  • Update Known Issues
2018-01-24v.25John Hartfiel
  • Release 2017.4
2018-01-10v.24John Hartfiel
  • Update Known Issues
2017-12-20v.23John Hartfiel
  • Typo correction
  • Update HW Module Table Description
2017-11-21

v.19

John Hartfiel
  • Design Update
2017-11-20v.18John Hartfiel
  • Design Update
  • Add Variants with 128MB Flash
2017-11-13v.16John Hartfiel
  • Update Carrier sections
2017-11-06v.15John Hartfiel
  • Typo corrected
2017-10-23v.13John Hartfiel
  • Update Key Features section
  • Style Update Additional Software section
2017-10-19
v.9
John Hartfiel
  • Release 2017.2
2017-09-11v.1Initial release

All
Document change history.

Legal Notices

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.




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