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title | Design Revision History |
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Date | Vivado | Project Built | Authors | Description |
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2019-10-29 | 2018.3 | TE0820-test_board_noprebuilt-vivado_2018.3-build_09_20191029071045.zip TE0820-test_board-vivado_2018.3-build_09_20191029071028.zip | John Hartfiel | | 2019-08-0908-ß9 | 2018.3 | TE0820-test_board_noprebuilt-vivado_2018.3-build_07_20190809084040.zip TE0820-test_board-vivado_2018.3-build_07_20190809083901.zip | John Hartfiel | - bugfix fsbl (removed second PSU init)
| 2019-06-19 | 2018.3 | TE0820-test_board_noprebuilt-vivado_2018.3-build_06_20190619073300.zip TE0820-test_board-vivado_2018.3-build_06_20190619073243.zip | John Hartfiel | - new assembly variants
- USB2 only (change PS IP and device tree)
- FSBL changes
| 2019-04-01 | 2018.3 | TE0820-test_board_noprebuilt-vivado_2018.3-build_03_20190401130135.zip TE0820-test_board-vivado_2018.3-build_03_20190401130123.zip | John Hartfiel | - renamed ...D variantes to ...A
| 2019-02-21 | 2018.3 | TE0820-test_board_noprebuilt-vivado_2018.3-build_01_20190221103025.zip TE0820-test_board-vivado_2018.3-build_01_20190221102913.zip | John Hartfiel | - TE Script update
- rework of the FSBLs
- SI5338 CLKBuilder Pro Project
- some additional Linux features
- MAC from EEPROM
- new assembly variants
- remove special compiler flags, which was needed in 2018.2
| 2018-10-31 | 2018.2 | TE0820-test_board_noprebuilt-vivado_2018.2-build_03_20181031164506.zip TE0820-test_board-vivado_2018.2-build_03_20181031164452.zip | John Hartfiel | - new assembly variants
- update optional petalinux startup init script
| 2018-09-12 | 2018.2 | TE0820-test_board_noprebuilt-vivado_2018.2-build_03_20180912094615.zip TE0820-test_board-vivado_2018.2-build_03_20180912094558.zip | John Hartfiel | - correction:
- TE0820-03-4EV-1EA has 2GB DDR, now 2GB instead of 1GB is initialised
- small changes on DDR setup of TE0820-02-2EG-1EE
| 2018-08-15 | 2018.2 | TE0820-test_board-vivado_2018.2-build_01_20180706212937.zip TE0820-test_board_noprebuilt-vivado_2018.2-build_01_20180706212952.zip | John Hartfiel | - different design for REV03
- small petalinux changes
- IO renaming
- additional notes for FSBL generated with Win SDK
- changed *.bif
| 2018-06-19 | 2017.4 | TE0820-test_board-vivado_2017.4-build_10_20180619160713.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_10_20180619160728.zip | John Hartfiel | - bugfix board part files BANK1 MIO voltages
- Add "dummy" PS USB3 parameter so solve problems with some USB2 devices
| 2018-05-24 | 2017.4 | TE0820-test_board-vivado_2017.4-build_10_20180524151356.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_10_20180524151342.zip | John Hartfiel | - solved Linux Flash issue
- new assembly variant
| 2018-04-25 | 2017.4 | TE0820-test_board-vivado_2017.4-build_07_20180425134435.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_07_20180425134459.zip | John Hartfiel | | 2018-02-06 | 2017.4 | TE0820-test_board-vivado_2017.4-build_06_20180206203359.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_06_20180206203414.zip | John Hartfiel | | 2018-02-01 | 2017.4 | TE0820-test_board-vivado_2017.4-build_05_20180201084319.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_05_20180201094724.zip | John Hartfiel | | 2018-01-24 | 2017.4 | TE0820-test_board-vivado_2017.4-build_05_20180124085247.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_05_20180124085303.zip | John Hartfiel | - rework board part files
- solved USB, QSPI and PHy issue
| 2017-11-21 | 2017.2 | TE0820-test_board-vivado_2017.2-build_05_20171121160552.zip TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171121160606.zip | John Hartfiel | - solved SD SDX Cards Problem
- Separate csv name for all assembly variants
| 2017-11-20 | 2017.2 | TE0820-test_board-vivado_2017.2-build_05_20171120162931.zip TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171120162851.zip | John Hartfiel | | 2017-10-19 | 2017.2 | TE0820-test_board-vivado_2017.2-build_05_20171019104824.zip TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171019104837.zip | John Hartfiel | |
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title | Hardware Modules |
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Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
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TE0820-ES1 | es1 | REV01 | 1GB | 64MB | 4GB | NA | Not longer supported by vivado | TE0820-02-02EG-1E | 2eg_1e_1gb | REV02 | 1GB | 64MB | 4GB | NA | NA | TE0820-02-02EG-1E3 | 2eg_1e_1gb | REV02 | 1GB | 64MB | 4GB | 2.5 mm connectors | NA | TE0820-02-02CG-1E | 2cg_1e_1gb | REV02 | 1GB | 64MB | 4GB | NA | NA | TE0820-02-03EG-1E | 3eg_1e_1gb | REV02 | 1GB | 64MB | 4GB | NA | NA | TE0820-02-03EG-1E3 | 3eg_1e_1gb | REV02 | 1GB | 64MB | 4GB | 2.5 mm connectors | NA | TE0820-02-03CG-1E | 3cg_1e_1gb | REV02 | 1GB | 64MB | 4GB | NA | NA | TE0820-02-02EG-1EA | 2eg_1e_1gb | REV02 | 1GB | 128MB | 4GB | NA | NA | TE0820-02-02EG-1EL | 2eg_1e_1gb | REV02 | 1GB | 128MB | 4GB | 2.5 mm connectors | NA | TE0820-02-02CG-1EA | 2cg_1e_1gb | REV02 | 1GB | 128MB | 4GB | NA | NA | TE0820-02-03EG-1EA | 3eg_1e_1gb | REV02 | 1GB | 128MB | 4GB | NA | NA | TE0820-02-03EG-1EL | 3eg_1e_1gb | REV02 | 1GB | 128MB | 4GB | 2.5 mm connectors | NA | TE0820-02-03CG-1EA | 3cg_1e_1gb | REV02 | 1GB | 128MB | 4GB | NA | NA | TE0820-02-04CG-1EA | 4cg_1e_1gb | REV02 | 1GB | 128MB | 4GB | NA | NA | TE0820-03-04EV-1EA | 4ev_1e_2gb | REV03 | 2GB | 128MB | 4GB | NA | NA | TE0820-03-02CG-1EA | 2cg_1e_2gb | REV03 | 2GB | 128MB | 4GB | NA | NA | TE0820-03-02EG-1EA | 2eg_1e_2gb | REV03 | 2GB | 128MB | 4GB | NA | NA | TE0820-03-02EG-1EL | 2eg_1e_2gb | REV03 | 2GB | 128MB | 4GB | 2.5 mm connectors | NA | TE0820-03-03CG-1EA 1EA | 3cg_1e_2gb | REV03 | 2GB | 128MB | 4GB | NA | NA | TE0820-03-04CG-1EA 1EA | 4cg_1e_2gb | REV03 | 2GB | 128MB | 4GB | NA | NA | TE0820-03-03EG-1EA 1EA | 3eg_1e_2gb | REV03 | 2GB | 128MB | 4GB | NA | NA | TE0820-03-03EG-1EL | 3eg_1e_2gb | REV03 | 2GB | 128MB | 4GB | 2.5 mm connectors | NA | TE0820-03-2AI21FA | 2cg_1i_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA | TE0820-03-2BE21FL | 2eg_1e_2gb | REV03 | 2GB | 128MB | 8GB | 2.5 mm connectors | NA | TE0820-03-3AI210A | 3cg_1i_2gb | REV03 | 2GB | 128MB | 0GB | NA | NA | TE0820-03-3BE21FA | 3eg_1e_2gb | REV03 | 2GB | 128MB | 4GB | NA | NA | TE0820-03-3BE21FL | 3eg_1e_2gb | REV03 | 2GB | 128MB | 4GB | 2.5 mm connectors | NA | TE0820-03-02CG-1ED | 2cg_1e_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA | TE0820-03-2AE21FA | 2cg_1e_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA | TE0820-03-2BE21FA | 2eg3eg_1e_2gb | REV03 | 2GB | 128MB | 4GB | 8GB | NA 2.5 mm connectors | NA | TE0820-03- | 2AI21FA 3AE21FA | 2cg3cg_ | 1i1e_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA | TE0820-03- | 2BE21FL 3AI21FA | 2eg3cg_ | 1e1i_2gb | REV03 | 2GB | 128MB | 8GB | 2.5 mm connectors NA | NA | TE0820-03- | 3AI210A 4AE21FA | 3cg4cg_ | 1i1e_2gb | REV03 | 2GB | 128MB | 0GB 8GB | NA | NA | TE0820-03- | 3BE21FA 4DE21FA | 3eg4ev_1e_2gb | REV03 | 2GB | 128MB | 4GB 8GB | NA | NA | TE0820-03- | 3BE21FL 4DI21FA | 3eg4ev_ | 1e1i_2gb | REV03 | 2GB | 128MB | 4GB | 2.5 mm connectors 8GB | NA | NA |
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Design supports following carriers:
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For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
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Type | Location | Notes |
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Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts | SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI | PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
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Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Create Linux (bl31.elf, uboot.elf and image.ub) with exported HDF
- HDF is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
- Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
- Generate Programming Files with HSI/SDK
- Run on Vivado TCL: TE::sw_run_hsi
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
Note: See SDK Projects
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Date | Document Revision | Authors | Description |
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Page info |
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| modified-date |
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| modified-date |
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dateFormat | yyyy-MM-dd |
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prefix | v. |
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| | 2019-08-09 | v.55 | John Hartfiel | | 2019-06-19 | v.54 | John Hartfiel | - design changes
- new variants
| 2019-04-01 | v.53 | John Hartfiel | - some notes
- renamed ..D variants to ...A
| 2018-09-21 | v.47 | John Hartfiel | - 2018.3 release finished (include design reworks)
| | v.43 | John Hartfiel | - Update Design files for 2GB variants
- rebuilt petalinux for optional init script
| | v.41 | John Hartfiel | - Update Design files for 2GB variants
| | v.40 | John Hartfiel | | | v.38 | John Hartfiel | | | v.34 | John Hartfiel | | | v.29 | John Hartfiel | | 2018-02-06 | v.27 | John Hartfiel | | 2018-01-29 | v.26 | John Hartfiel | | 2018-01-24 | v.25 | John Hartfiel | | 2018-01-10 | v.24 | John Hartfiel | | 2017-12-20 | v.23 | John Hartfiel | - Typo correction
- Update HW Module Table Description
| 2017-11-21 | v.19 | John Hartfiel | | 2017-11-20 | v.18 | John Hartfiel | - Design Update
- Add Variants with 128MB Flash
| 2017-11-13 | v.16 | John Hartfiel | | 2017-11-06 | v.15 | John Hartfiel | | 2017-10-23 | v.13 | John Hartfiel | - Update Key Features section
- Style Update Additional Software section
| 2017-10-19 | v.9 | John Hartfiel | | 2017-09-11 | v.1 | | Initial release |
| All | Page info |
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| modified-users |
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| modified-users |
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