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Template Revision 3.1
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"
Template Change history: Template Change history: - 3.02 to 3.1
- New general notes for temperature range to "Recommended Operating Conditions"
- 3.01 to 3.02
- add again fix table of content with workaround to use it for pdf and wiki
- Export Link for key features examples
- Notes for different Types (with and without Main FPGA)
- Export Link for Signals, Interfaces and Pins examples
- Notes for different Types (Modul, Modul Hypride, Evalboard, Carrier)
- 3.0 to 3.01
- remove fix table of content and page layout ( split page layout make trouble with pdf export)
- changed and add note to signal and interfaces, to on board periphery section
- ...(not finished)
- 2.13 to 3.00
- → separation of Carrier/Module and evaluation kit TRM
- 2.14 to 2.15
- add excerpt macro to key features
- 2.13 to 2.14
- add fix table of content
- add table size as macro
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Important General Note:
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Note for Download Link of the Scroll ignore macro: |
Overview
The Trenz Electronic TE0865 is an industrial/extended grade module based on Xilinx Zunq UltraScale+ MPSoC. The TE0865 is equipped with 4x 2GB DDR4 SDRAM connected to Programmable Logic(PL) and 5x 2GB DDR4 SDRAM connected to Processing System(PS), 8 GB eMMC, 2x 64MB Quad SPI Flash, Gigabit Ethernet Transceiver, USB Transceiver, Ultra micro power terminal and an Intel MAx 10 as system controller CPLD.
Refer to http://trenz.org/te0865-info for the current online version of this manual and other available documentation.
Key Features
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- SoC/FPGA
- Package: C1760
- Device: ZU11, ZU17, ZU19*
- Engine: EG*
- Speed: -1, -2,*, **
- Temperature: I, E,*, **
- RAM/Storage
- Low Power DDR4 on PS
- Data width: 16bit
- Size: def. 2GB*
- Speed: 3200 (MT/s) ***
- Low Power DDR4 on PL
- Data width: 16bit
- Size: def. 2GB*
- Speed:***
- eMMC
- Data width: 8Bit
- size: def. 8GB *
- Dual QSPI boot Flash in dual parallel mode (size depends on assembly version)
- Data width: 8bit
- size: def. 64MB *
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- On Board
- Intel Max 10 as CPLD
- 6x MEMS Oscillator
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3340C)
- Interface
- 214 x PS I/Os
- 96x HD I/Os
- 416x HP I/Os
- 4x PS GTR
- 3x Samtec Accelerate HD B2B connector
- 78x MIOs
- Power
- 12V input supply voltage
- Variable Bank IO Power Input
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
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Block Diagram
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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.
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Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name. Example: TE0812 Block Diagram |
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All created DrawIOs should be named according to the Module name: Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD |
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anchor | Figure_OV_BD |
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title | TE0865 block diagram |
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draw.io Diagram |
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diagramName | TE0865_OV_BD |
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diagramWidth | 641 |
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revision | 6 |
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Main Components
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Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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anchor | Figure_OV_MC |
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title | TE0865 main components |
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draw.io Diagram |
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diagramName | TE0865_OV_MC |
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- ZYNQ Ultrascale+ MPSoC FPGA, U30
- PL DDR4 SDRAM, U9, U10, U28, U29
- PS DDR4 SDRAM, U5...U8, U11
- Intel MAX 10 FPGA, U46
- eMMC RAM, U1
- Dual QSPI Flash, U32, U33
- Crypto Authentication IC, U19
- OPTIGA Trust M Authentication IC, U16
- EEPROM MAC Address, U14
- USB2.0 Transceiver, U2
- Gigabit Ethernet Transceiver, U17
- B2B Connector, J2
- B2B Connector, J3
- B2B Connector, J1
- B2B Connector, J4
- Power Terminal, J5
Initial Delivery State
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Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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anchor | Table_OV_IDS |
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title | Initial delivery state of programmable devices on the module |
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sortEnabled | false |
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cellHighlighting | true |
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Storage device name | Content | Notes |
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Quad SPI Flash | Not Programmed |
| EEPROM | Programmed | MAC Address | System Controller CPLD | Programmed | Intel MAX 10 | PL DDR4 SDRAM | Not Programmed |
| PS DDR4 SDRAM | Not Programmed |
| eMMC | Not Programmed |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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anchor | Table_OV_CNTRL |
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title | Controller signal. |
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orientation | portrait |
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sortDirection | ASC |
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sortEnabled | false |
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cellHighlighting | true |
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Function | Schematic | Connected to |
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Name | B2B/Connector | Direction | Description |
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Boot Mode |
Enable | Reset | JTAGSEL | | MODE0...3 | B2B, J3A | Input |
| Reset | PERST0 | B2B, J1B | Input |
| PGOOD | PG_VCCINT | CPLD, U46 |
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| Power Enable | EN_VCCINT | CPLD, U46 |
PGOOD | ...
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Signals, Interfaces and Pins
B2B SoC/FPGA IOs
B2B JTAG Interface
B2B ETH Interface
B2B USB Interface
SD Card Connector
SMA Connector
MIO
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MIO section only for SoC devices with dedicated MIO, otherwhise remove this section |
MIO Pins
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Only for SoC Modules(Xilinx MIO, for Intel and MicroChip SoC please change MIO to syntax of the manufacturer). you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.
MIO Pins are only for SoC like Zynq, U+Zynq and Versal, for other FPGA modules remove this chapter
Example:
Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
Scroll Title |
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anchor | Table_SIP_B2B |
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title | General PL I/O to B2B connectors information |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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JTAG Interface
JTAG access to the UltraScale+ MPsoC FPGA through B2B connector J3B.
Scroll Title |
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anchor | Table_SIP_JTG |
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title | JTAG pins connection |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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JTAG Signal | B2B Connector |
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TMS | J3B- D59 | TDI | J3B- D57 | TDO | J3B- D58 | TCK | J3B- D56 |
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JTAG access to the system controller CPLD, Intel MAX10 FPGA(U46) through B2B connector J2B.
Scroll Title |
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anchor | Table_SIP_JTG |
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title | JTAG pins connection |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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JTAG Signal | B2B Connector |
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TCK_MAX10 | J2B- D56 | TMS_MAX10 | J2B- D57 | TDO_MAX10 | J2B- D58 | TDI_MAX10 | J2B- D59 | JTAGEN | Pulled Up |
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MIO Pins
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: MIO Pin | Connected to | B2B | Notes |
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MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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anchor | Table_SIP_MIOs |
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title | MIOs pins |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MIO Pin | Connected to | Notes |
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MIO0...5 | QSPI Flash, U32 |
| MIO6...11 | QSPI, Flash, 33 |
| MIO13...22 | eMMC, U1 |
| MIO23 | B2B, J2A | U_INIT | MIO24...25 | B2B, J3B | I2C U via Voltage Transform, U15 | MIO26...27 | B2B, J2A | UART0_RX | MIO28...29 | B2B, J2A | UART1_RX | MIO30...31 | B2B, J2A | I2C M via Voltage Transform, U12 | MIO32...37 | B2B, J2A | GPIO0...5 | MIO38 | B2B, J2A | M_INIT | MIO39...42 | B2B, J2B | SD | MIO43 | B2B, J2A | PS_RSTn | MIO44...51 | B2B, J2A | SD | MIO52...63 | USB2.0, U2 | USB2.0 | MIO64...77 | ETH PHY, U17 | ETH PHY |
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Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: Test Point | Signal | B2B | Notes |
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10 | PWR_PL_OK | J2-120 |
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anchor | Table_SIP_TPs |
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title | Test Points Information |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Test Point | Signal | Notes |
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TP1...2 | +12.0V |
| TP3...4 | +3.3V |
| TP5...6 | +3.3V_SW |
| TP7...8 | +2.3V |
| TP9...10 | +1.8V |
| TP11...12 | +1.8V_AUX |
| TP13...14 | +1.8V_VCCADC |
| TP15...16 | +0.85V_VCCINT |
| TP17...18 | +1.2V_PL_DDR |
| TP19...20 | +2.5V_PL_DDR |
| TP21...22 | +0.85V_GTR_AVCC_PS |
| TP23...24 | +1.8V_GTR_AVTT_PS |
| TP25...26 | +1.8V_AUX_PS |
| TP27...28 | +1.2V_PLL_PS |
| TP29...30 | +1.2V_PS_DDR |
| TP31...32 | +2.5V_PS_DDR |
| TP33...34 | VREFA_DDR_PS |
| TP35...36 | VREFA_DDR_PL |
| TP37...38 | VTT_DDR_PS |
| TP39...40 | VTT_DDR_PL |
| TP41...42 | +0.9V_GTH_AVCC |
| TP43...44 | +1.8V_GTH_AUX |
| TP45...46 | +1.2V_GTH_AVTT |
| TP47...48 | +0.9V_GTY_AVCC |
| TP49...50 | +1.8V_GTY_AUX |
| TP51...52 | +1.2V_GTY_AVTT |
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On-board Peripherals
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection Example: #ClockSources, #CPLD, #QuadSPIFlash |
Scroll Title |
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anchor | Table_OBP |
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title | On board peripherals |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Chip/Interface | Designator | Notes |
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Intel MAX 10 | U46 |
| PL DDR4 SDRAM | U9, U10, U28, U29 |
| PS DDR4 RAM | U5...U8, U11 |
| Dual QSPI Flash | U32, U33 |
| eMMC RAM | U1 |
| USB2.0 Transceiver | U2 |
| Gigabit Ethernet Transceiver | U17 |
| EEPROM | U14 |
| Crypto Authentication | U19 |
| OPTIGA Authentication | U16 |
| MEMS Oscillator, |
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CPLD
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Note |
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Link always to CPLD Documentation, because CPLD Firmware can be changed during the time. Describe used device type and basic Pin connection to B2B and Main FPGA |
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Quad SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
Scroll Title |
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anchor | Table_OBP_SPI |
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title | Quad SPI interface MIOs and pins |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MIO Pin | Schematic | U?? Pin | Notes |
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Crypto Authentication
OPTIGA Authentication
EEPROM
Scroll Title |
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anchor | Table_OBP_EEP |
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title | I2C EEPROM interface MIOs and pins |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MIO Pin | Schematic | U?? Pin | Notes |
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Scroll Title |
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anchor | Table_OBP_I2C_EEPROM |
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title | I2C address for EEPROM |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MIO Pin | I2C Address | Designator | Notes |
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PL DDR4 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.
- Part number:
- Supply voltage:
- Speed:
- NOR Flash
- Temperature:
PS DDR4 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.
- Part number:
- Supply voltage:
- Speed:
- NOR Flash
- Temperature:
Ethernet
Scroll Title |
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anchor | Table_OBP_ETH |
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title | Ethernet PHY to Zynq SoC connections |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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U?? Pin | Signal Name | Connected to | Signal Description | Note |
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eMMC
Scroll Title |
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anchor | Table_OBP_eMMC |
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title | eMMC Information |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Clock Sources
MIO Pin | Connected to | B2B | Notes |
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MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI Scroll Title |
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anchor | Table_SIPOBP_MIOsCLK |
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title | Test Points InformationOsillators |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MIO Pin | Connected to | B2B | Notes |
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Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.
Example:
Designator | Description | Frequency | Note |
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| MHz |
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| MHz |
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| KHz |
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Power and Power-On Sequence
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power supply with minimum current capability of xx A for system startup is recommended.
Power Consumption
Test Point | Signal | B2B | Notes |
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10 | PWR_PL_OK | J2-120 Scroll Title |
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anchor | Table_SIPPWR_TPsPC |
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title | Test Points InformationPower Consumption |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Test Point | Signal | Connected to | Notes |
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TP1...2 | +12.0V | Regulators | TP3...4 | +3.3V | TP5...6 | +3.3V_SW | TP7...8 | +2.3V | TP9...10 | +1.8V | TP11...12 | +1.8V_AUX | TP13...14 | +1.8V_VCCADC | TP15...16 | +0.85V_VCCINT | TP17...18 | +1.2V_PL_DDR | TP19...20 | +2.5V_PL_DDR | TP21...22 | +0.85V_GTR_AVCC_PS | TP23...24 | +1.8V_GTR_AVTT_PS | TP25...26 | +1.8V_AUX_PS | TP27...28 | +1.2V_PLL_PS | TP29...30 | +1.2V_PS_DDR | TP31...32 | +2.5V_PS_DDR | TP33...34 | VREFA_DDR_PS | TP35...36 | VREFA_DDR_PL | TP37...38 | VTT_DDR_PS | TP39...40 | VTT_DDR_PL | TP41...42 | +0.9V_GTH_AVCC | TP43...44 | +1.8V_GTH_AUX | TP45...46 | +1.2V_GTH_AVTT | TP47...48 | +0.9V_GTY_AVCC | TP49...50 | +1.8V_GTY_AUX | TP51...52 | +1.2V_GTY_AVTT |
On-board Peripherals
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Notes :
In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection
Power Input Pin | Typical Current |
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VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
Scroll Title |
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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Scroll Ignore |
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draw.io Diagram |
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border | false |
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diagramName | TE0865_PWR_PD |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | |
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lbox | true |
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diagramWidth | 641 |
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revision | 1 |
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Scroll Only |
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Image Added |
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Power-On Sequence
Scroll Title |
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anchor | Figure_PWR_PS |
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title | Power Sequency |
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Scroll Ignore |
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draw.io Diagram |
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border | false |
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diagramName | TE0865_PWR_PS |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | |
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lbox | true |
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diagramWidth | 641 |
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revision | 1 |
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Scroll Only |
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Image Added |
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Voltage Monitor Circuit
Scroll Title |
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anchor | Figure_PWR_VMC |
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title | Voltage Monitor Circuit |
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Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Power Rails
Example: #ClockSources, #CPLD, #QuadSPIFlash Scroll Title |
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anchor | Table_PWR_OBPPR |
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title | On board peripheralsModule power rails. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Chip/Interface | Designator | Notes |
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Power and Power-On Sequence
Page properties |
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
- Power on-sequence
- Power distribution
- Voltage monitoring circuit
Power Rail Name | B2B J1 Pin | B2B J2 Pin | B2B J3 Pin | B2B J4 Pin | Direction | Notes |
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VCCIO_67 | D10 | - | - | - | In |
| VCCIO_66 | D20 | - | - | - | In |
| VCCIO_64 | D35 | - | - | - | In |
| VCCIO_65 | D45 | - | - | - | In |
| VCCIO_91 | - | A6, | - | - | In |
| VCCIO_90 | - | B10 | - | - | In |
| VCCIO_89 | - | A21 | - | - | In |
| V_IO_CFG | - | A45 | - | - | In |
| +1.2V_PL_DDR | - | B44 | - | - | Out |
| VCCIO_68 | - | C29 | - | - | In |
| VCCIO_88 | - | D44 | - | - | In |
| +3.3V | - | D60 | - | - | Out |
| +1.8V | - |
| D60 | - | Out |
|
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Bank Voltages
Power Supply
Power supply with minimum current capability of xx A for system startup is recommended.
Power Consumption
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anchor | Table_PWR_PC |
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title | Power Consumption |
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style | widths | sortByColumn | 1 |
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cellHighlighting | true |
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Power Input Pin | Typical Current |
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VIN | TBD* |
* TBD - To Be Determined
Power Distribution Dependencies
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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draw.io Diagram |
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border | false |
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diagramName | TE0865_PWR_PD |
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simpleViewer | false |
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width | links | auto |
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tbstyle | hidden |
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diagramDisplayName | lbox | true |
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diagramWidth | 641 |
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revision | 1 |
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Power-On Sequence Scroll Title |
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anchor | FigureTable_PWR_PSBV |
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title | Power SequencyZynq SoC bank voltages. |
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border | false |
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diagramName | TE0865_PWR_PS |
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simpleViewer | false |
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width | links | auto |
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tbstyle | hidden |
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diagramDisplayName | lbox | true |
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diagramWidth | 641 |
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revision | 1 |
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Voltage Monitor Circuit
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anchor | Figure_PWR_VMC |
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title | Voltage Monitor Circuit |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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| Schematic Name | | Notes |
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64 HP | VCCIO_64 | max 1.8 V |
| 65 HP | VCCIO_65 | max 1.8 V |
| 66 HP | VCCIO_66 | max 1.8 V |
| 67 HP | VCCIO_67 | max 1.8 V |
| 68 HP | VCCIO_68 | max 1.8 V |
| 69 HP | VCCIO_69 | 1.2 V |
| 70 HP | VCCIO_70 | 1.2 V |
| 71 HP | VCCIO_71 | 1.2 V |
| 88 HD | VCCIO_88 | max 3.3V | ZU17 Bank 90 HD | 89 HD | VCCIO_88 | max 3.3 V | ZU17 Bank 91 HD | 90 HD | VCCIO_88 | max 3.3V | ZU17 Bank 93 HD | 91 HD | VCCIO_88 | max 3.3V | ZU17 Bank 94 HD | 128 GTY | MGTAVCC_L | 0.9 V |
| 129 GTY | MGTAVCC_L | 0.9 V |
| 224 GTH | MGTAVCC_RS | 0.9 V |
| 225 GTH | MGTAVCC_RS | 0.9 V |
| 228 GTH | MGTAVCC_RN | 0.9 V |
| 229 GTH | MGTAVCC_RN | 0.9 V |
| 500 PSMIO | VCCO_PSIO0_500 | 1.8 V |
| 501 PSMIO | VCCO_PSIO0_501 | max 3.3 V |
| 502 PSMIO | VCCO_PSIO0_502 | 1.8 V |
| 504 PSDDR | VCCO_PSDDR_504 | 1.2 V |
| 505 PSGTR | PS_MGTRAVCC | 0.85 V |
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Power Rails
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anchor | Table_PWR_PR |
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title | Module power rails. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
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Bank Voltages
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anchor | Table_PWR_BV |
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title | Zynq SoC bank voltages. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Board to Board Connectors
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- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
Include Page |
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| PD:6 x 6 SoM LSHM B2B Connectors |
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| PD:6 x 6 SoM LSHM B2B Connectors |
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Technical Specifications
Absolute Maximum Ratings
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anchor | Table_TS_AMR |
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title | PS absolute maximum ratings |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Symbols | Description | Min | Max | Unit |
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| V |
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| V |
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| °C |
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Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
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anchor | Table_TS_ROC |
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title | Recommended operating conditions. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortEnabled | false |
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cellHighlighting | true |
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Parameter | Min | Max | Units | Reference Document |
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| V | See ???? datasheets. |
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| V | See ???? datasheet. |
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| V | See ???? datasheet. |
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| V | See ???? datasheet. |
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| V | See ???? datasheet. |
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| V | See ???? datasheet. |
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| V | See ???? datasheet. |
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| °C | See ???? datasheet. |
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| °C | See ???? datasheet. |
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Components are mainly classified in 3 temperature groups, according to range specifications: commercial: 0°C - 75°C extended: 0°C - 85°C industrial: -40°C - 85°C
Classification of the module can be locked up here: Article Number Information i.e.: TE0803-03-5D"I"21-AS (The I indicates industrial)
The actual operation temperature range depends on the FPGA/SoC design/utilization and cooling, as well as other variables. Please note: These are only indications!
Physical Dimensions
PCB thickness: 2 mm.
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anchor | Figure_TS_PD |
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title | Physical Dimension |
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draw.io Diagram |
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border | false |
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diagramName | TE0865_TS_PD |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | |
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lbox | true |
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diagramWidth | 641 |
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revision | 2 |
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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Currently Offered Variants
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anchor | Table_VCP_SO |
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title | Trenz Electronic Shop Overview |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Revision History
Hardware Revision History
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anchor | Figure_RV_HRN |
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title | Board hardware revision number. |
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border | false |
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diagramName | TE0865_RV_HRN |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | |
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lbox | true |
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diagramWidth | 132 |
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revision | 2 |
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anchor | Table_RH_HRH |
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title | Hardware Revision History |
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orientation | portrait |
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repeatTableHeaders | default |
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style | |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Revision | Changes | Documentation Link |
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2021-04-15 | REV01 | Initial Release |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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anchor | Table_RH_DCH |
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title | Document change history. |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Revision | Contributor | Description |
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Page info |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| Page info |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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showVersions | false |
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| Page info |
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infoType | Modified by |
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type | Flat |
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showVersions | false |
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| | -- | all | Page info |
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infoType | Modified users |
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type | Flat |
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showVersions | false |
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Disclaimer
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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|