Page History

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Date	Vivado	Project Built	Authors	Description
2018-10-31	2018.2	TE0820-test_board_noprebuilt-vivado_2018.2-build_03_20181031164506.zip TE0820-test_board-vivado_2018.2-build_03_20181031164452.zip	John Hartfiel	new assembly variants update optional petalinux startup init script
2018-09-12	2018.2	TE0820-test_board_noprebuilt-vivado_2018.2-build_03_20180912094615.zip TE0820-test_board-vivado_2018.2-build_03_20180912094558.zip	John Hartfiel	correction: TE0820-03-4EV-1EA has 2GB DDR, now 2GB instead of 1GB is initialised small changes on DDR setup of TE0820-02-2EG-1EE
2018-08-15	2018.2	TE0820-test_board-vivado_2018.2-build_01_20180706212937.zip TE0820-test_board_noprebuilt-vivado_2018.2-build_01_20180706212952.zip	John Hartfiel	different design for REV03 small petalinux changes IO renaming additional notes for FSBL generated with Win SDK changed *.bif
2018-06-19	2017.4	TE0820-test_board-vivado_2017.4-build_10_20180619160713.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_10_20180619160728.zip	John Hartfiel	bugfix board part files BANK1 MIO voltages Add "dummy" PS USB3 parameter so solve problems with some USB2 devices
2018-05-24	2017.4	TE0820-test_board-vivado_2017.4-build_10_20180524151356.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_10_20180524151342.zip	John Hartfiel	solved Linux Flash issue new assembly variant
2018-04-25	2017.4	TE0820-test_board-vivado_2017.4-build_07_20180425134435.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_07_20180425134459.zip	John Hartfiel	new assembly variants
2018-02-06	2017.4	TE0820-test_board-vivado_2017.4-build_06_20180206203359.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_06_20180206203414.zip	John Hartfiel	solved JTAG/Linux issue
2018-02-01	2017.4	TE0820-test_board-vivado_2017.4-build_05_20180201084319.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_05_20180201094724.zip	John Hartfiel	board part csv update
2018-01-24	2017.4	TE0820-test_board-vivado_2017.4-build_05_20180124085247.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_05_20180124085303.zip	John Hartfiel	rework board part files solved USB, QSPI and PHy issue
2017-11-21	2017.2	TE0820-test_board-vivado_2017.2-build_05_20171121160552.zip TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171121160606.zip	John Hartfiel	solved SD SDX Cards Problem Separate csv name for all assembly variants
2017-11-20	2017.2	TE0820-test_board-vivado_2017.2-build_05_20171120162931.zip TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171120162851.zip	John Hartfiel	solved SD WP Problem
2017-10-19	2017.2	TE0820-test_board-vivado_2017.2-build_05_20171019104824.zip TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171019104837.zip	John Hartfiel	initial release

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Module Model	Board Part Short Name	PCB Revision Support	DDR	QSPI Flash	Others	Notes
~~TE0820-ES1~~	~~es1~~	REV01	1GB	64		use slower DDR speed Xilinx has stopped ES1 support with 2018.2, please use 2017.4 reference design for ES1
TE0820-02-2EG-1E	2eg_1e	REV02	1GB	64
TE0820-02-2EG-1E3	2eg_1e	REV02	1GB	64	2.5 mm Samtec connectors
TE0820-02-2EG-1EA	2eg_1e	REV02	1GB	128	TE0820-02-2EG-1EE	2eg_1ee	REV02	2GB	128
TE0820-02-2EG-1EL	2eg_1e	REV02	1GB	128	2.5 mm Samtec connectors
TE0820-02-2CG-1E	2cg_1e	REV02	1GB	64
TE0820-02-2CG-1EA	2cg_1e	REV02	1GB	128
TE0820-02-3EG-1E	3eg_1e	REV02	1GB	64
TE0820-02-3EG-1E3	3eg_1e	REV02	1GB	64	2.5 mm Samtec connectors
TE0820-02-3EG-1EA	3eg_1e	REV02	1GB	128
TE0820-02-3EG-1EL	3eg_1e	REV02	1GB	128	2.5 mm Samtec connectors
TE0820-02-3CG-1E	3cg_1e	REV02	1GB	64
TE0820-02-3CG-1EA	3cg_1e	REV02	1GB	128
TE0820-02-4CG-1EA	4cg_1e	REV02	1GB	128
TE0820-03-4EV-1EA	4ev_1e_2gb	REV03	2GB	12864
TE0820-0203-3CG2CG-1EA	3cg2cg_1e_2gb	REV02REV03	1GB2GB	128
TE0820-0203-4CG2EG-1EA	4cg2eg_1e_2gb	REV02REV03	1GB2GB	128
TE0820-03-4EV2EG-1EA1EL	4ev2eg_1e_2gb	REV03	2GB	128	2.5 mm Samtec connectors

Design supports following carriers:

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Type	Location	Notes
SI5338	<design name>/misc/Si5338	SI5338 Project with current PLL Configuration
init_script	<design name>/misc/init_script	optional init script for SD card

Prebuilt

HTML

<!-- 

<table width="100%">
<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
</table>
-->

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Date

Document Revision

Authors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Page info

	current-version
	current-version
prefix	v.

Page info

	modified-user
	modified-user

Update Design files for 2GB variants
rebuilt petalinux for optional init script

12 Sept 2018

v.41

John Hartfiel

Update Design files for 2GB variants

11 Jul 2018

v.4140

John Hartfiel

add notes to ES1

06 Jul 2018

v.38

John Hartfiel

2018.2 release finished

19 Jun 2018

v.34

John Hartfiel

Design Files Update

13 Feb 2018

v.29

John Hartfiel

Design Files Update

2018-02-06

v.27

John Hartfiel

Design Files Update

2018-01-29

v.26

John Hartfiel

Update Known Issues

2018-01-24

v.25

John Hartfiel

Release 2017.4

2018-01-10

v.24

John Hartfiel

Update Known Issues

2017-12-20

v.23

John Hartfiel

Typo correction
Update HW Module Table Description

2017-11-21

v.19

John Hartfiel

Design Update

2017-11-20

v.18

John Hartfiel

Design Update
Add Variants with 128MB Flash

2017-11-13

v.16

John Hartfiel

Update Carrier sections

2017-11-06

v.15

John Hartfiel

Typo corrected

2017-10-23

v.13

John Hartfiel

Update Key Features section
Style Update Additional Software section

2017-10-19

v.9

John Hartfiel

Release 2017.2

2017-09-11

v.1

Page info

	created-user
	created-user

Initial release

All

Page info

	modified-users
	modified-users

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Trenz Electronic Documentation

Versions Compared

Old Version 41

New Version 42

Key

Prebuilt