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Template Revision 3.1
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"
Template Change history: Template Change history: - 3.02 to 3.1
- New general notes for temperature range to "Recommended Operating Conditions"
- 3.01 to 3.02
- add again fix table of content with workaround to use it for pdf and wiki
- Export Link for key features examples
- Notes for different Types (with and without Main FPGA)
- Export Link for Signals, Interfaces and Pins examples
- Notes for different Types (Modul, Modul Hypride, Evalboard, Carrier)
- 3.0 to 3.01
- remove fix table of content and page layout ( split page layout make trouble with pdf export)
- changed and add note to signal and interfaces, to on board periphery section
- ...(not finished)
- 2.13 to 3.00
- → separation of Carrier/Module and evaluation kit TRM
- 2.14 to 2.15
- add excerpt macro to key features
- 2.13 to 2.14
- add fix table of content
- add table size as macro
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Important General Note:
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----------------------------------------------------------------------- |
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Note for Download Link of the Scroll ignore macro: |
Overview
The Trenz Electronic TE0865-01-DGE43FA is a high-performance MPSoC module integrating a Xilinx Zynq UltraScale+ ZU17EG (other assembly options for the FPGA are available), 8 GByte DDR4 SDRAM with ECC on PS, 8 GByte DDR4 SDRAM on PL, 256 MByte Flash memory for configuration and operation, Gigabit Ethernet PHY, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking connections.
The prototype configuration of TE0865 will be available with many configuration options available that you can customize to meet your specific needs.
All parts are at least extended temperature range of 0°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Refer to http://trenz.org/te0865-info for the current online version of this manual and other available documentation.
Key Features
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- SoC/FPGA
- Package: C1760
- Device: ZU11, ZU17, ZU19*
- Engine: EG*
- Speed: -1, -2,*, **
- Temperature: I, E,*, **
- RAM/Storage
- DDR4 on PS with ECC
- Data width: 64 bit
- Size: def. 2GB*
- Speed: 3200 (MT/s) ***
- DDR4 on PL
- Data width: 64 bit
- Size: def. 2GB*
- Speed: 3200 (MT/s) ***
- eMMC
- Data width: 8 Bit
- size: def. 8 GB *
- Dual QSPI boot Flash in dual parallel mode (size depends on assembly version)
- Data width: 8bit
- size: def. 64MB *
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- On Board
- Intel Max 10 FPGA as CPLD
- 6x MEMS Oscillator
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3340C)
- Interface
- 214 x PS I/Os
- 96x HD I/Os
- 416x HP I/Os
- 4x PS GTR
- 3x Samtec Accelerate HD B2B connector
- 78x MIOs
- Power
- 12V input supply voltage
- Variable Bank IO Power Input
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
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Block Diagram
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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.
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Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name. Example: TE0812 Block Diagram |
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All created DrawIOs should be named according to the Module name: Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD |
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anchor | Figure_OV_BD |
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title | TE0865 block diagram |
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diagramName | TE0865_OV_BD |
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diagramWidth | 641 |
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revision | 26 |
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Main Components
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Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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anchor | Figure_OV_MC |
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title | TE0865 main components |
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draw.io Diagram |
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border | false |
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diagramName | TE0865_OV_MC |
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- ZYNQ Ultrascale+ MPSoC FPGA, U30
- PL DDR4 SDRAM, U9, U10, U28, U29
- PS DDR4 SDRAM, U5...U8, U11
- Intel MAX 10 FPGA, U46
- eMMC RAM, U1
- Dual QSPI Flash, U32, U33
- Crypto Authentication IC, U19
- OPTIGA Trust M Authentication IC, U16
- EEPROM MAC Address, U14
- USB2.0 Transceiver, U2
- Gigabit Ethernet Transceiver, U17
- B2B Connector, J2
- B2B Connector, J3
- B2B Connector, J1
- B2B Connector, J4
- Power Terminal, J5
- Configurable Regulator, U20
Initial Delivery State
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Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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anchor | Table_OV_IDS |
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title | Initial delivery state of programmable devices on the module |
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orientation | portrait |
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Storage device name | Content | Notes |
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Quad SPI Flash | Not Programmed |
| EEPROM | Programmed | MAC Address | System Controller CPLD | Programmed | Intel MAX 10 | PL DDR4 SDRAM | Not Programmed |
| PS DDR4 SDRAM | Not Programmed |
| eMMC | Not Programmed |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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anchor | Table_OV_CNTRL |
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title | Controller signal. |
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orientation | portrait |
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Function | Schematic | Connected to | Direction | Description |
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Boot Mode | MODE0...3 | B2B, J3A | Input |
| Reset | PERST0 | B2B, J1B | Input |
| PGOOD | PG_VCCINT | CPLD, U46 | Output |
| Power Enable | EN_VCCINT | CPLD, U46 | Input |
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Signals, Interfaces and Pins
Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
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anchor | Table_SIP_B2B |
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title | General PL I/O to B2B connectors information |
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orientation | portrait |
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Bank | Type | B2B Connector | I/O Signal Count | Voltage | Notes |
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64 | HP | JM2 | 48x Single Ended, 24x LVDS Pairs | Variable | Max voltage 1.8V | 64 | HP | JM2 | 2x Single Ended | Variable | Max voltage 1.8V | 65 | HP | JM2 | 18x Single Ended, 9x LVDS Pairs | Variable | Max voltage 1.8V | 65 | HP | JM3 | 16x Single Ended, 8x LVDS Pairs | Variable | Max voltage 1.8V | 66 | HP | JM1 | 48x Single Ended, 24x LVDS Pairs | Variable | Max voltage 1.8V | 500 | MIO | JM1 | 8x Single Ended | 1.8V |
| 501 | MIO | JM1 | 6x Single Ended | 3.3V |
| 505 | GTR | JM3 | 16x Single Ended, 8x LVDS Pairs | - | 4x Lanes | 505 | GTR CLK | JM3 | 1x differential Clock | - |
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For detailed information about the pin-out, please refer to the Pin-out table.
MGT Lanes
The Xilinx Zynq UltraScale+ device used on the TE0820 module has 4 GTR transceivers. All 4 are wired directly to B2B connector JM3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:
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anchor | Table_SIP_MGT |
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title | MGT Lanes connection |
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Lane | Bank | Signal Name | B2B Pin | Note |
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0 | 505 | - B505_RX0_P
- B505_RX0_N
- B505_TX0_P
- B505_TX0_N
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| 1 | 505 | - B505_RX1_P
- B505_RX1_N
- B505_TX1_P
- B505_TX1_N
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| 2 | 505 | - B505_RX2_P
- B505_RX2_N
- B505_TX2_P
- B505_TX2_N
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| 3 | 505 | - B505_RX3_P
- B505_RX3_N
- B505_TX3_P
- B505_TX3_N
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There are 3 clock sources for the GTR transceivers. B505_CLK0 is connected directly to B2B connector JM3, so the clock can be provided by the carrier board. Clocks B505_CLK1 and B505_CLK3 are provided by the on-board clock generator (U10). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.
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anchor | Table_SIP_MGTCLK |
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title | MGT Clock Sources Information |
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orientation | portrait |
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sortDirection | ASC |
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cellHighlighting | true |
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Clock signal | Bank | Connected to | Notes |
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B505_CLK0_P | 505 | B2B, JM3-31 | Supplied by the carrier board | B505_CLK0_N | 505 | B2B, JM3-33 | Supplied by the carrier board | B505_CLK1_P | 505 | U10, CLK2A | On-board Si5338A | B505_CLK1_N | 505 | U10, CLK2B | On-board Si5338A | B505_CLK2_P | 505 | N/A | Not connected | B505_CLK2_N | 505 | N/A | Not connected | B505_CLK3_P | 505 | U10, CLK1A | On-board Si5338A | B505_CLK3_N | 505 | U10, CLK1B | On-board Si5338A |
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JTAG Interface
JTAG access to the UltraScale+ MPsoC FPGA through B2B connector J3B.
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anchor | Table_SIP_JTG |
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title | JTAG pins connection |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortEnabled | false |
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cellHighlighting | true |
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JTAG Signal | B2B Connector |
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TMS | J3B- D59 | TDI | J3B- D57 | TDO | J3B- D58 | TCK | J3B- D56 |
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JTAG access to the system controller CPLD, Intel MAX10 FPGA(U46) through B2B connector J2B.
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anchor | Table_SIP_JTG |
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title | JTAG pins connection |
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orientation | portrait |
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sortDirection | ASC |
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JTAG Signal | B2B Connector |
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TCK_MAX10 | J2B- D56 | TMS_MAX10 | J2B- D57 | TDO_MAX10 | J2B- D58 | TDI_MAX10 | J2B- D59 | JTAGEN | Pulled Up |
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I2C Addresses
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anchor | Table_SIP_I2CADD |
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title | I2C addresses |
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orientation | portrait |
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cellHighlighting | true |
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I2C Address | Designator | Notes |
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0x53 | U14 | EEPROM | 0x30 | U16 | OPTIGA Trust M | 0x4E | U20 | Configurable Regulator |
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MIO Pins
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: MIO Pin | Connected to | B2B | Notes |
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MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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anchor | Table_SIP_MIOs |
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title | MIOs pins |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MIO Pin | Connected to | Notes |
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MIO0...5 | QSPI Flash, U32 |
| MIO6...11 | QSPI, Flash, U33 |
| MIO13...22 | eMMC, U1 |
| MIO23 | B2B, J2A | U_INIT | MIO24...25 | B2B, J3B | I2C via Voltage Transform, U15 | MIO26...27 | B2B, J2A | UART0_RX | MIO28...29 | B2B, J2A | UART1_RX | MIO30...31 | B2B, J2A | I2C via Voltage Transform, U12 | MIO32...37 | B2B, J2A | GPIO0...5 | MIO38 | B2B, J2A | M_INIT | MIO39...42 | B2B, J2B | SD | MIO43 | B2B, J2A | PS_RSTn | MIO44...51 | B2B, J2A | SD | MIO52...63 | USB2.0, U2 | USB2.0 | MIO64...77 | ETH PHY, U17 | ETH PHY |
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Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: Test Point | Signal | B2B | Notes |
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10 | PWR_PL_OK | J2-120 |
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anchor | Table_SIP_TPs |
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title | Test Points Information |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortEnabled | false |
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cellHighlighting | true |
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Test Point | Signal | Notes |
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TP1...2 | +12.0V |
| TP3...4 | +3.3V |
| TP5...6 | +3.3V_SW |
| TP7...8 | +2.3V |
| TP9...10 | +1.8V |
| TP11...12 | +1.8V_AUX |
| TP13...14 | +1.8V_VCCADC |
| TP15...16 | +0.85V_VCCINT |
| TP17...18 | +1.2V_PL_DDR |
| TP19...20 | +2.5V_PL_DDR |
| TP21...22 | +0.85V_GTR_AVCC_PS |
| TP23...24 | +1.8V_GTR_AVTT_PS |
| TP25...26 | +1.8V_AUX_PS |
| TP27...28 | +1.2V_PLL_PS |
| TP29...30 | +1.2V_PS_DDR |
| TP31...32 | +2.5V_PS_DDR |
| TP33...34 | VREFA_DDR_PS |
| TP35...36 | VREFA_DDR_PL |
| TP37...38 | VTT_DDR_PS |
| TP39...40 | VTT_DDR_PL |
| TP41...42 | +0.9V_GTH_AVCC |
| TP43...44 | +1.8V_GTH_AUX |
| TP45...46 | +1.2V_GTH_AVTT |
| TP47...48 | +0.9V_GTY_AVCC |
| TP49...50 | +1.8V_GTY_AUX |
| TP51...52 | +1.2V_GTY_AVTT |
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On-board Peripherals
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection Example: #ClockSources, #CPLD, #QuadSPIFlash |
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anchor | Table_OBP |
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title | On board peripherals |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Chip/Interface | Designator | Notes |
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Intel MAX 10 CPLD | U46 |
| PL DDR4 SDRAM | U9, U10, U28, U29 |
| PS DDR4 SDRAM | U5...U8, U11 |
| Dual QSPI Flash | U32, U33 |
| eMMC Memory | U1 |
| USB2.0 Transceiver | U2 |
| Gigabit Ethernet Transceiver | U17 |
| EEPROM | U14 |
| Crypto Authentication | U19 |
| OPTIGA Authentication | U16 |
| MEMS Oscillator | U3, U4, U13, U18, U31, U34 |
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System Controller CPLD
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Note |
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Link always to CPLD Documentation, because CPLD Firmware can be changed during the time. Describe used device type and basic Pin connection to B2B and Main FPGA |
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The TE0865 is equipped with an Intel MAX 10 as System Controller CPLD (U46). Please check further information in the TE0865 CPLD page.
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anchor | Table_OBP_CPLD |
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title | CPLD pin connections |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Bank | Schematic | Connectced to | Notes |
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Bank 1A | VCCIO1A | 3.3V |
| Bank 1B | TCK_MAX10 | B2B, J2B |
| TMS_MAX10 | B2B, J2B |
| TDO_MAX10 | B2B, J2B |
| TDI_MAX10 | B2B, J2B |
| VCCIO1B | 3.3V |
| Bank 2 | EN_VTT_DDR_PL | Regulator, U26 |
| EN_+2.5V_PL_DDR | Regulator, U22 | Enable Power DDR4 PL | EN_+1.2V_PL_DDR | Regulator, U24 | Enable Power DDR4 PL | PG_+1.2V_PL_DDR | Regulator, U24 | Power Good DDR4 PL | EN_+1.8V_AUX_PS | Regulator, U43 |
| SC_EXT_1...4 | B2B, J2B |
| PG_VCCINT | Regulator, U20 | Configurable Regulator | LTM_FAULT | Regulator, U20 | Configurable Regulator | M_SDA | I2C Bus | B2B, J2A via level shifter (U12) | M_SCL | I2C Bus | B2B, J2A via level shifter (U12) | MR | B2B, J2B Regulator, U51 |
| Bank 3 | SMB_ALERTn | Regulator, U20 | Configurable Regulator | PG_+2.5V_PL_DDR | Regulator, U22 | Power Good DDR4 PL | LTM_RUNP_EN | Regulator, U20 | Configurable Regulator | M_SDA | I2C Bus | B2B, J2A via level shifter (U12) | M_SCL | I2C Bus | B2B, J2A via level shifter (U12) | RST_SYSn | Diod, U53B | Reset | EN_+0.9V_GTH_AVCC | Regulator, U35 |
| EN_+0.9V_GTY_AVCC | Regulator, U38 |
| PG_+1.2V_PS_DDR | Regulator, U25 | Power Good DDR4 PS | PG_+0.9V_GTH_AVCC | Regulator, U35 |
| PG_+0.9V_GTY_AVCC | Regulator, U38 |
| EN_+3.3V_SW | Regulator, U52 | Secondary Power | EN_+1.2V_PLL_PS | Regulator, U42 |
| PG_+1.8V_GTR_AVTT_PS | Regulator, U47 |
| PG_+1.8V | Regulator, U41 |
| EN_+2.5V_PS_DDR | Regulator, U23 | Enable Power DDR4 PS | PG_+1.2V_GTY_AVTT | Regulator, U39 |
| EN_+1.2V_GTY_AVTT | Regulator, U39 |
| M_INT | B2B, J2A |
| EN_+1.8V_VCCADC | Regulator, U49 |
| PG_+0.85V_GTR_AVCC_PS | Regulator, U48 |
| EN_VTT_DDR_PS | Regulator, U27 |
| EN_+1.8V | Regulator, U41 |
| EN_+1.8V_GTY_AUX | Regulator, U40 |
| PG_+2.3V | Regulator, U45 |
| Bank 6 | VCCIO6 | 3.3V |
| Bank 5 | EN_+1.8V_GTR_AVTT_PS | Regulator, U47 |
| EN_+1.8V_GTH_AUX | Regulator, U37 |
| EN_+1.8V_AUX | Regulator, U50 |
| EN_+1.2V_GTH_AVTT | Regulator, 36 |
| PG_+1.2V_GTH_AVTT | regulator, U36 |
| +3.3V_SW | eMMC, U1 |
| EN_+1.2V_PS_DDR | Regulator, U25 | Power Good DDR4 PS | EN_+0.85V_GTR_AVCC_PS | Regulator, U48 |
| PG_+1.2V_GTH_AVTT | Regulator, U48 |
| EN_VCCINT | Regulator, U20 |
| EN_+2.3V | Regulator, U45 |
| PG_+1.8V_AUX | Regulator, U50 |
| PG_+2.5V_PS_DDR | Regulator, U23 | Power Good DDR4 PS |
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Dual QSPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
The TE0865 is equipped with dual 128 Mb (256 Mb) QSPI flash memory, U32 and U33 for configuration and operation storage.
Scroll Title |
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anchor | Table_OBP_SPI |
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title | Quad SPI interface MIOs and pins |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Pin | Schematic | Notes |
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U32 | CLK | MIO0 |
| DI/IO0 | MIO4 |
| DO/IO1 | MIO1 |
| nWP/IO2 | MIO2 |
| nHOLD/IO3 | MIO3 |
| nCS | MIO5 |
| U33 | CLK | MIO12 |
| DI/IO0 | MIO8 |
| DO/IO1 | MIO9 |
| nWP/IO2 | MIO10 |
| nHOLD/IO3 | MIO11 |
| nCS | MIO7 |
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eMMC Memory
The TE0865 is equipped with an eMMC Flash memory IC(U1) connected to the PS MIO pins MIO13..MIO22. The eMMC chips IS21ES08G-JCLI (FLASH - NAND Speicher-IC (64 Gb x 1) MMC ) is used.
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anchor | Table_OBP_eMMC |
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title | eMMC connections |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Pin | Schematic | Connected to | Notes |
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U32 | CLK | MMC-CCLK | MIO22 |
| nRESET | RST_PERn | - | PS_RSTn, PS_SYSn | CMD | MMC-CMD | MIO21 |
| DAT0...7 | MMCD0...7 | MIO13...20 |
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Gigabit Ethernet
On-board Gigabit Ethernet PHY (U17) is provided with Marvell Alaska 88E1512 IC (U17). The Ethernet PHY RGMII interface is connected to the ZynqMP Ethernet3 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the ETH is supplied from an on-board 25.00 MHz oscillator (U18).
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anchor | Table_SIP_ETH |
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title | GigaBit Ethernet connection |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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Pin | Schematic | Connected to | Note |
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MDIP0...3 | PHY_MDI0...3 | B2B, J3A |
| MDC | ETH_MDC | MIO76 |
| MDIO | ETH_MDIO | MIO77 |
| S_IN | S_IN | N.C |
| S_OUT | S_OUT | N.C |
| TXD0..3 | ETH_TXD0...3 | MIO65...68 |
| TX_CTRL | ETH_TXCTL | MIO69 |
| TX_CLK | ETH_TXCK | MIO64 |
| RXD0...3 | ETH_RXD0...3 | MIO71...74 |
| RX_CTRL | ETH_RXCTL | MIO75 |
| RX_CLK | ETH_RXCK | MIO70 |
| LED1 | PHY_LED1 | B2B, J3A |
| RESETn | ETH_RST | MIO24 |
| XTAL_IN | ETH_CLK | Oscillator, U18 | Input Clock of ETH Transciever | nRESET | RST_PERn | B2B, J2A | PS_RSTn, PS_SYSn |
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USB2.0 Transceiver
Hi-speed USB2.0 transceiver (U2) is provided with USB3340 from Microchip. The transceiver is connected to the PS MIO via MIO52..63. The I/O voltage is fixed at 3.3V (VBAT) and PHY reference clock input is supplied from the on-board 24.00 MHz oscillator (U13).
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anchor | Table_SIP_USB |
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title | General overview of the USB PHY signals |
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orientation | portrait |
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sortDirection | ASC |
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Pin | Schematic | MIO | B2B Name | Notes |
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RESETB | RST_PERn |
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| RST_PERn | VBAT | VBAT |
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| 3.3V | CPEN | USB_CPEN |
| B2B, J3A |
| VBUS | USB_VBUS |
| B2B, J3A |
| ID | USB_ID |
| B2B, J3A |
| DP, DM | USB_DP USB_ DM |
| B2B, J3A |
| REFCLK | USB_CLK24_PHY | - | - | 24.00MHz from on-board oscillator (U13). | REFSEL[0..2] | - | - | - | Reference clock frequency select, all set to 1.8V selects 24 MHz. | DATA0...7 | USB_DATA0...7 | MIO 56,57,54, 59...62 | - | Connected to 1.8V, selects reference clock operation mode. | STP | USB_STP | MIO58 | - | USB data lines routed to B2B connector JM3 pins 47 and 49. | NXT | USB_NXT | MIO55 | - | External USB power switch active high enable signal, routed to JM3 pin 17. | DI | USB_DI | MIO53 | - | Connect to USB VBUS via a series of resistors, see reference schematics, routed to JM3 pin 55. | CLKOUT | USB_CLKOUT | MIO52 | - | For an A-device connect to ground, for a B-device left floating. routed from JM3 pin 23. |
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EEPROM
There is an EEPROM (U14) provided on the module TE0865 for storing MAC Address. The EEPROM has the I2C bus address 0x53.
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anchor | Table_OBP_EEP |
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title | I2C EEPROM interface MIOs and pins |
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MIO Pin | Schematic | U25 Pin | Notes |
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MIO39 | I2C_SDA | SDA |
| MIO38 | I2C_SCL | SCL |
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Crypto Authentication
The TE0865 is equipped with an Authentication IC, ATECC608A (U19) includes an EEPROM array which can be used for storage of up to 16 keys, certificates, miscellaneous read/write, read-only or secret data, consumption logging, and security configurations. Access to the various sections of memory can be restricted in a variety of ways and then the configuration can be locked to prevent changes.
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anchor | Table_OBP_AUTH |
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title | Crypto Authentication connection |
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orientation | portrait |
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repeatTableHeaders | default |
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cellHighlighting | true |
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Pin | Schematic | Connected to | Notes |
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SDA | M_SDA | B2B, J2A | M_SDA_PS | SCL | M_SDA | B2B, J2A | M_SCL_PS |
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OPTIGA Authentication
The TE0865 is equipped with an OPTIGA Trust M IC, SLS32AIA010MH (U16). The OPTIGA Trust M comes with up to 10kB of user memory that can be used to store X.509 certificates and data. OPTIGA Trust M is based on Common Criteria (CC) Certified EAL6+ (high) hardware enabling it to prevent physical attacks on the device itself and providing high assurance that the keys or arbitrary data stored cannot be accessed by an unauthorized entity. The OPTIGA Trust M is connected via I2C with address of 0x30.
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anchor | Table_OBP_OPTIGA |
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title | OPTIGA Authentication connection |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortEnabled | false |
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cellHighlighting | true |
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Pin | Schematic | Connected to | Notes |
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SDA | M_SDA | B2B, J2A |
| SCL | M_SDA | B2B, J2A |
| RST | RST_SECn | B2B, J2A | PS_RSTn |
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PL DDR4 SDRAM
Page properties |
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE0865 SoM has four 2GB volatile DDR4 SDRAM ICs connected to Programmable Logic(PL) for operations, storing and streaming data.
- Part number: MT40A1G16RC-062E
- Supply voltage: 1.2V
- Speed: 3200 MT/s
- Temperature: -40 ~ 95 °C
PS DDR4 SDRAM
Page properties |
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE0865 SoM has five 2GB volatile DDR4 SDRAM ICs connected to Processing System (PS) for operations, storing and streaming data.
- Part number: MT40A1G16RC-062E
- Supply voltage: 1.2V
- Speed: 3200 MT/s
- Temperature: -40 ~ 95 °C
Clock Sources
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anchor | Table_OBP_CLK |
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title | Osillators |
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orientation | portrait |
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sortDirection | ASC |
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Designator | Description | Frequency | Note |
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U3 | MEMS Oscillator | 27 MHz | MGT_CLK0 | U4 | MEMS Oscillator | 100 MHz | MGT_CLK1 | U13 | MEMS Oscillator | 24 MHz | USB_CLK | U18 | MEMS Oscillator | 25 MHz | ETH_CLK | U31 | MEMS Oscillator | 200 MHz | DDR4 Clock | U34 | MEMS Oscillator | 33.33 MHz | PS REF CLK |
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Power and Power-On Sequence
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power supply with minimum current capability of 3.0 A for system startup is recommended.
Power Consumption
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anchor | Table_PWR_PC |
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title | Power Consumption |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortEnabled | false |
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cellHighlighting | true |
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Power Input Pin | Typical Current |
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VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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draw.io Diagram |
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border | false |
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diagramName | TE0865_PWR_PD |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | |
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lbox | true |
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diagramWidth | 641 |
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revision | 9 |
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Power-On Sequence
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anchor | Figure_PWR_PS |
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title | Power Sequency |
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draw.io Diagram |
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border | false |
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diagramName | TE0865_PWR_PS |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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lbox | true |
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diagramWidth | 641 |
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revision | 3 |
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Voltage Monitor Circuit
The LTM4700 (U20) is a dual 50A or single 100A step-down µModule(power module) DC/DC regulator featuring remote configurability and telemetry-monitoring of power management parameters over standard I2C-based digital interface protocol.
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anchor | Figure_PWR_VMC |
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title | Voltage Monitor Circuit |
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draw.io Diagram |
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border | false |
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diagramName | TE0865_PWR_VMC |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | |
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lbox | true |
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diagramWidth | 641 |
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revision | 4 |
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Power Rails
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anchor | Table_PWR_PR |
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title | Module power rails. |
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orientation | portrait |
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sortDirection | ASC |
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cellHighlighting | true |
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Power Rail Name | B2B J1 Pin | B2B J2 Pin | B2B J3 Pin | B2B J4 Pin | Direction | Notes |
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VCCIO_67 | D10 | - | - | - | In |
| VCCIO_66 | D20 | - | - | - | In |
| VCCIO_64 | D35 | - | - | - | In |
| VCCIO_65 | D45 | - | - | - | In |
| VCCIO_91 | - | A6, | - | - | In |
| VCCIO_90 | - | B10 | - | - | In |
| VCCIO_89 | - | A21 | - | - | In |
| V_IO_CFG | - | A45 | - | - | In |
| +1.2V_PL_DDR | - | B44 | - | - | Out |
| VCCIO_68 | - | C29 | - | - | In |
| VCCIO_88 | - | D44 | - | - | In |
| +3.3V | - | D60 | - | - | Out |
| +1.8V | - |
| D60 | - | Out |
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Bank Voltages
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anchor | Table_PWR_BV |
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title | Zynq SoC bank voltages. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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| Schematic Name | | Notes |
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64 HP | VCCIO_64 | max 1.8 V |
| 65 HP | VCCIO_65 | max 1.8 V |
| 66 HP | VCCIO_66 | max 1.8 V |
| 67 HP | VCCIO_67 | max 1.8 V |
| 68 HP | VCCIO_68 | max 1.8 V |
| 69 HP | VCCIO_69 | 1.2 V |
| 70 HP | VCCIO_70 | 1.2 V |
| 71 HP | VCCIO_71 | 1.2 V |
| 88 HD | VCCIO_88 | max 3.3V | ZU17 Bank 90 HD | 89 HD | VCCIO_88 | max 3.3 V | ZU17 Bank 91 HD | 90 HD | VCCIO_88 | max 3.3V | ZU17 Bank 93 HD | 91 HD | VCCIO_88 | max 3.3V | ZU17 Bank 94 HD | 128 GTY | MGTAVCC_L | 0.9 V |
| 129 GTY | MGTAVCC_L | 0.9 V |
| 224 GTH | MGTAVCC_RS | 0.9 V |
| 225 GTH | MGTAVCC_RS | 0.9 V |
| 228 GTH | MGTAVCC_RN | 0.9 V |
| 229 GTH | MGTAVCC_RN | 0.9 V |
| 500 PSMIO | VCCO_PSIO0_500 | 1.8 V |
| 501 PSMIO | VCCO_PSIO0_501 | max 3.3 V |
| 502 PSMIO | VCCO_PSIO0_502 | 1.8 V |
| 504 PSDDR | VCCO_PSDDR_504 | 1.2 V |
| 505 PSGTR | PS_MGTRAVCC | 0.85 V |
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Board to Board Connectors
Page properties |
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- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
Include Page |
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| PD:6 x 6 SoM LSHM B2B Connectors |
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| PD:6 x 6 SoM LSHM B2B Connectors |
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Include Page |
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| 7.5 x 10 ADM6/ADF6 B2B Connectors |
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| 7.5 x 10 ADM6/ADF6 B2B Connectors |
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Technical Specifications
Absolute Maximum Ratings
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anchor | Table_TS_AMR |
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title | PS absolute maximum ratings |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Symbols | Description | Min | Max | Unit |
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VCCR | Input Supply Voltage | 5.75 | 16 | V | T_STG | Storage Temperature | -40 | 85 | °C |
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Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Scroll Title |
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anchor | Table_TS_ROC |
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title | Recommended operating conditions. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Parameter | Min | Max | Units | Reference Document |
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VCCR | 11.5 | 12.5 | V | See LTM4700 (U20) datasheet. | T_OPT | 0 | 85 | °C | See components datasheet |
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Components are mainly classified in 3 temperature groups, according to range specifications: commercial: 0°C - 75°C extended: 0°C - 85°C industrial: -40°C - 85°C
Classification of the module can be locked up here: Article Number Information i.e.: TE0803-03-5D"I"21-AS (The I indicates industrial)
The actual operation temperature range depends on the FPGA/SoC design/utilization and cooling, as well as other variables. Please note: These are only indications!
Physical Dimensions
PCB thickness: 2 mm.
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anchor | Figure_TS_PD |
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title | Physical Dimension |
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Scroll Ignore |
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draw.io Diagram |
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border | false |
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diagramName | TE0865_TS_PD |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | |
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lbox | true |
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diagramWidth | 641 |
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revision | 2 |
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Scroll Only |
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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Currently Offered Variants
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anchor | Table_VCP_SO |
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title | Trenz Electronic Shop Overview |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Revision History
Hardware Revision History
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anchor | Figure_RV_HRN |
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title | Board hardware revision number. |
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draw.io Diagram |
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border | false |
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diagramName | TE0865_RV_HRN |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | |
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lbox | true |
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diagramWidth | 132 |
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revision | 2 |
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Scroll Only |
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Scroll Title |
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anchor | Table_RH_HRH |
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title | Hardware Revision History |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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cellHighlighting | true |
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Date | Revision | Changes | Documentation Link |
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2021-04-15 | REV01 | Initial Release |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
Page properties |
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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anchor | Table_RH_DCH |
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title | Document change history. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Revision | Contributor | Description |
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Page info |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| Page info |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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showVersions | false |
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| Page info |
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infoType | Modified by |
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type | Flat |
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showVersions | false |
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| | -- | all | Page info |
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infoType | Modified users |
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type | Flat |
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showVersions | false |
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Disclaimer
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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