Page History
...
| Signal | B2B Pin |
|---|---|
| TCK | J2: 119 |
| TDI | J2: 115 |
| TDO | J2: 117 |
| TMS | J2: 113 |
| Note |
|---|
JTAGEN pin in JM1 should be kept low or grounded for normal operation. |
| Clock | Frequency | IC | FPGA | Notes |
|---|---|---|---|---|
| PS CLK | 33.3333 MHz | U14 | PS_CLK | PS Subsystem main clock |
| 10/100/1000 Mbps ETH PHY reference | 25 MHz | U10 | - | |
| USB PHY reference | 52 MHz | U12 | - |
...
Overview
Content Tools