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  • Xilinx Zynq-7000 XC7Z045-2FFG900I SoC
  • Rugged for shock and high vibration
  • Large number of configurable I/Os are provided via rugged high-speed stacking strips
  • Dual ARM Cortex-A9 MPCore
    • 1 GByte RAM (32-Bit 32bit wide DDR3) connected to PS
    • 2 GByte RAM (64bit wide DDR3) connected to PL
    • 32 MByte QSPI Flash memory
    • 2 x Hi-Speed USB2 ULPI transceiver PHY
    • 2 x Gigabit (10/100/1000 Mbps) Ethernet transceiver PHY
    • 4 GByte eMMC (optional up to 64 GByte)
  • Lattice MachXO2 HC 4000 System Controller CPLD
    • 40 GPIO's available to user on B2B connector
  • 2 x MAC-address EEPROMsEEPROM
  • Serial user EEPROMOptional 2x 64 MByte HyperFLASH or 2x 8 MByte HyperRAM (max 2x 32 MByte HyperRAM)
  • Temperature compensated RTC (real-time clock)
  • Si5338A programmable quad PLL clock generator for GTX transceiver clocks
  • Plug-on module with 3 x 160-pin high-speed strips
    • 16 GTX high-performance transceiver
    • 2x 4x GT transceiver clock inputs
    • 254 FPGA I/O's (125 LVDS pairs)
  • On-board high-efficiency switch-mode DC-DC converters
  • System management
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • Evenly-spread supply pins for good signal integrity
  • User LED

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Scroll Title
anchorFigure_1
titleFigure 1: TE0783-01 block diagram
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Main Components

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