Page History

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Overview

The Trenz Electronic TE0782 TE0783 is a high-performance, industrial-grade SoM (System on Module) with industrial temperature range based on Xilinx Zynq-7000 SoC (XC7Z035, XC7Z045 or XC7Z100).

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Refer to http://trenz.org/te0782te0783-info for the current online version of this manual and other available documentation.

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Main Components

1. Xilinx Zynq UltraScale+ MPSoC-7000 SoC, U1
2. Lattice Semiconductor MachXO2 1200HC CPLD, U144Gbit DDR3L SDRAM, U19
3. 4Gbit DDR3L SDRAM, U19U10
4. 4Gbit DDR3L SDRAM, U10
5. I²C voltage translator, U25
6. Intersil ISL12020MIRZ Real Time Clock, U17
7. Microchip USB3320C USB PHY transceiver, U4
8. Microchip USB3320C USB PHY transceiver, U8
9. U8
10. 4Gbit DDR3L SDRAM, U9
11. 4Gbit DDR3L SDRAM, U14
12. 4Gbit DDR3L SDRAM, U12
13. SI5338A programmable quad PLL clock generator, U2
14. SiTime SiT8008 25SiTime SiT8008 52.000000 MHz oscillator, U7
15. 32 MByte QSPI Flash memory, U38
16. SiTime SiT8008 33.333333 MHz oscillator, U61
17. SI5338A programmable quad PLL clock generator, U2
18. SiTime SiT8008 25.000000 MHz oscillator, U3
19. U3
20. Lattice Semiconductor MachXO2 4000HC CPLD, U32
21. Microchip 128Kbit I²C EEPROM, U26
22. Microchip 2Kbit I²C MAC EEPROM, U22
23. TPS780180300 LDO @1.8V backup battery voltage, U21
24. TCA9406DCUR I²C voltage level shifter, U25
25. Intersil ISL12020MIRZ Real Time Clock, U17
26. Microchip USB3320C USB PHY transceiver, U4
27. SiTime SiT8008 52.000000 MHz oscillator, U7
28. 74AVCH4T245 voltage level tranlator, U30
29. TPS74801RGW TPS74801 LDO @1.5V, U23
30. 32 MByte QSPI Flash memory, U38
31. LT quad 4A PowerSoC DC-DC converter (@1.0V), U13
32. LT quad 4A PowerSoC DC-DC converter (@3.3V, @1,8V, @1.2V_MGT, @1.0V_MGT), U16
33. TPS74801RGW LDO @1.5V_PL, U20
34. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J2
35. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J3
36. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J1
37. Marvell Alaska 88E1512 Gigabit Ethernet PHY, 20Micron Technology 4 GByte eMMC, U28
38. Marvell Alaska 88E1512 Gigabit Ethernet PHY, U18
39. Micron Technology 4 GByte eMMC, U15
40. Microchip 128Kbit I²C EEPROM, U26
41. Microchip 2Kbit I²C MAC EEPROM, U24
42. Microchip 2Kbit I²C MAC EEPROM, U22
43. Texas Instruments TXS02612RTWR SDIO Port Expander, U29
44. SiTime SiT8008 25.000000 MHz oscillator, U11
45. DSC1123CI2 Low-Jitter Precision LVDS Oscillator, U31
46. SiTime SiT8008 33.333333 MHz oscillator, U33TPS51206 DDR reference voltage and termination regulator, U6
47. TPS799 LDO @1.8V_MGT, U5SiTime SiT8008 25.000000 MHz oscillator,
48. U11TPS799 LDO @VCCAUX_IO (1.8V), U35

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module

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4 of the 7 boot mode strapping pins (MIO2 ... MIO8) of the Xilinx Zynq-7000 SoC device are hardware programmed on the board, 3 of them are set be the SC CPLD firmware. They are evaluated by the Zynq device soon after the 'PS_POR' signal is deasserted to begin the boot process (see section "Boot Mode Pin Settings" of Xilinx manual UG585).

The TE0782 TE0783 board is programmed in the SC CPLD firmware to boot initially from the on-board QSPI Flash memory U38. See section Bootmode in the TE0782 TE0783 SC CPLD reference Wiki page.

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Zynq-7000 SoC's I/O banks signals connected to the B2B connectors:

Table 2: General overview of board to board I/O signals

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The Xilinx Zynq-7000 SoC used on the TE0782 TE0783 module has 16 MGT transceiver lanes. All of them are wired directly to B2B connectors J1 and J3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane with data transmission rates up to 12.5Gb/s per lane (Xilinx GTX transceiver). Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Table 3: MGT lanes

There are 2 clock sources for the GTX transceivers. MGT_CLK1 and MGT_CLK4 are connected directly to B2B connector J3 and J1, so the clock can be provided by the carrier board. Clocks MGT_CLK0, MGT_CLK3, MGT_CLK5 and MGT_CLK6 are provided by the on-board clock generator (U2). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.

Table 4: MGT reference clock sources

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JTAG access to the Xilinx Zynq-7000 is provided through B2B connector J3.

Table 5: Zynq JTAG interface signals

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JTAG access to the LCMXO2-1200HC System Controller CPLD U14 is provided through B2B connector J3.

Table 6: System Controller CPLD JTAG interface signals

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Special purpose pins are connected to System Controller CPLD and have following default configuration:

Table 7: System Controller CPLD special purpose pins.

See also TE0782 TE0783 CPLD reference Wiki page.

Default PS MIO Mapping

Table 8: Zynq PS MIO mapping

Gigabit Ethernet

The TE0782 TE0783 is equipped with two Marvell Alaska 88E1512 Gigabit Ethernet PHYs (U18 (ETH1) and U20 (ETH2)). The transceiver PHY of ETH1 is connected to the Zynq PS Ethernet GEM0. The I/O Voltage is fixed at 1.8V for HSTL signaling. The reference clock input for both PHYs is supplied from an on board 25MHz oscillator (U11), the 125MHz output clock of both PHYs are connected to Zynq's PL bank 35.

ETH1 PHY connection:

Table 9: General overview of the Gigabit Ethernet1 PHY signals

ETH2 PHY connection:

Table 10: General overview of the Gigabit Ethernet2 PHY signals

USB Interface

The TE0782 TE0783 is equipped with two USB PHY's USB3320 from Microchip (U4 (USB0) and U8 (USB1)). The ULPI interface of USB0 is connected to the Zynq PS USB0, ULPI interface of USB1 to Zynq PS USB1. The I/O Voltage is fixed at 1.8V.

The reference clock input of both PHY's is supplied from an on board 52MHz oscillator (U7).

USB0 PHY connection:

Table 11: General overview of the Gigabit Ethernet2 PHY signals

USB1 PHY connection:

Table 12: General overview of the Gigabit Ethernet2 PHY signals

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I²C addresses for on-board components:

Table 13: Address table of the I²C bus slave devices

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The System Controller CPLD (U14) is provided by Lattice Semiconductor LCMXO2-1200HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.

See also TE0782 TE0783 CPLD reference Wiki page.

eMMC Flash Memory

eMMC Flash memory device (U15) is connected to the Zynq PS MIO bank 500 pins MIO10..MIO15. eMMC chips MTFC4GMVEA-4M IT (Flash NAND-IC 2x 16 Gbit) is used with 4 GByte of memory density.

DDR4 Memory

By default TE0782TE0783-02 01 module has two 16-bit wide IM (Intelligent Memory) IM4G16D3FABG-125I DDR3L SDRAM (DDR3-1600 Speedgrade) chips arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM.

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Two Microchip 24AA025E48 serial EEPROMs (U22, U24) contain globally unique 48-bit node address, which are compatible with EUI-48(TM) specification. The devices are organized as two blocks of 128 x 8 Kbit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. The MAC address EEPROMS areaccessible over I²C bus (see also section I²C interface).

Configuration EEPROM

The TE0782 TE0783 board contains one EEPROM (U26) for configuration and general user purposes. The EEPROMs is provided by Microchip 24LC128-I/ST with 128 KBit memory density, the EEPROM is areaccessible over I²C bus (see also section I²C interface).

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Once running, the frequency and other parameters can be changed by programming the device using the I²C bus connected between the FPGA (master) and clock generator (slave). For this, proper I²C bus logic has to be implemented in FPGA.

Table 14: General overview of the on-board quad clock generator I/O signals

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The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

Table 15: Reference clock signals

On-board LEDs

Table 16: On-board LEDs

Power and Power-on Sequence

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Power supply with minimum current capability of 3A for system startup is recommended.

Power Consumption

Table 17: Power consumption

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See also Xilinx datasheet DS191 for additional information. User should also check related base board documentation when intending base board design for TE0782 TE0783 module.

Power-On Sequence

The TE0820 SoM meets the recommended criteria to power up the Xilinx Zynq chip properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.

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See Xilinx datasheet DS925 for additional information. User should also check related carrier board documentation when choosing carrier board design for TE0715 module.

Power Rails

Table 18: Module power rails

Bank Voltages

Table 19: Module I/O bank voltages

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Board to Board Connectors

The TE0782 TE0783 SoM has three 160-pin double-row ASP-122952-01  Samtec connectors on the bottom side which mate with ASP-122953-01 Samtec connectors on the baseboard. Mating height is 5 mm.

Variants Currently In Production

Technical Specifications

Absolute Maximum Ratings

Table 20: Module absolute maximum ratings

Recommended Operating Conditions

Table 21: Recommended operating conditions

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Revision History

Hardware Revision History

Table 22: Hardware revision history table

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Document Change History

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Table 23: Document change history

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