Page History

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#1 Changed PLL (U5) from Si5345A-B to Si5345A-D-GM.

Type: Schematic Change

Reason:  Updated to new PLL revision.

Impact: None. Minor changes in electrical characteristics. For more information take a look at AN1006-Si534x-8x-RevB-RevD-Differences.

#1 Changed inverted buffer SN74LVC1G06DRL to not inverted buffer SN74LVC1G07DRL (U16A/U16B).

Type: Schematic Change

Reason:  Harmonize logic with other module series.

Impact: Logic state change for LED D1.

#5 Added diode (D3) between U41 pin 3 net MR and voltage rail LP_DCDC.

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Reason: Protect manual reset pin.

Impact: None.

#1

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Improved voltage rail VTT layout and added decoupling capacitor (C213 ... C215

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).

Type: Schematic Change

Reason: VTT layout and decoupling improvement.

Impact:Improved VTT voltage rail reliabililty.

#1 Replaced DDR4 memory chips to use bigger chip sizes.

Type: PCB Change

Reason: Increase DDR4 usage flexibility.

Impact: None. More DDR4 Chips are usable.

#6 Enabled DDR4 test usage via connecting

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DDR4-TEN

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signals together for DDR4 memory (U2, U3, U9, U12) and pulling them down low via 499 Ohm resistor (R103)

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. Added testpoint (TP3) for signal DDR4-TEN.

Type: Schematic Change

Reason: Enable DDR4 test improvement.

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Reason: Remote sense option.

Impact: None.

#17 Added additional decoupling capacitors C136, C149...C151, C155, C156, C201...C212, C216

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...C234, 

Type: Schematic Change

Reason: Improve decoupling.

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Reason: BOM Optimization.

Impact: None.

#19 Changed 10 µF capacitor (C65

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... C67) from 16 V, 0603 to 10 V, 0401.

Type: Schematic Change

Reason: BOM Optimization.

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#28 Added Trenz address on PCB.

Type: PCB Change

Reason:  Required for export to UK.Improve product identification. (ED: ???)

Impact: None.

#28 Added CE-, UKCA-, RoHS-, and WEEE-logo.

Type: PCB Change

Reason: Required for export to UK. (ED: ???) Improve product classification.

Impact: None.

#29 Updated components from library.

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