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The B2B connectors J1 and J2 provide also access to the MGT - banks of the Zynq UltrascaleUltraScale+ MPSoC. There are 8 high-speed data lanes (Xilinx GTH / GTR transceiver) available composed as differential signaling pairs for both directions (RX/TX).
The MGT - banks have also clock input-pins which are exposed to the B2B connectors J2 and J3. Following MGT - lanes are available on the B2B connectors:
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Table 3: B2B connector pin-outs of available MGT - lanes of the MPSoC
1) Bank 224 only available at ZU4CG or ZU4EV MPSoC
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The Xilinx Zynq UltrascaleUltraScale+ MPSoC's PS configuration bank 503 control signal pins are accessible through B2B-connector J2.
For further information about the particular control signals and how to use and evaluate them, refer to the Xilinx Zynq UltrascaleUltraScale+ MPSoC TRM and UltraScale Architecture Configuration - User Guide.
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The Xilinx Zynq UltrascaleUltraScale+ MPSoC provides differential pairs for analog input values. The pins are exposed to B2B-connector J2.
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MIO | Signal Schematic Name | U7 Pin | MIO | Signal Schematic Name | U17 Pin | |
---|---|---|---|---|---|---|
0 | SPI Flash-SCK/M4 | B2 | 7 | SPI Flash-SCK | C2 | |
1 | SPI Flash-DQ1/M1 | D2 | 8 | SPI Flash-DQ0/M0 | D3 | |
2 | SPI Flash-DQ2/M2 | C4 | 9 | SPI Flash-DQ1/M1 | D2 | |
3 | SPI Flash-DQ3/M3 | D4 | 10 | SPI Flash-DQ2/M2 | C4 | |
4 | SPI Flash-DQ0/M0 | D3 | 11 | SPI Flash-DQ3/M3 | D4 | |
5 | SPI Flash-SCK | C2 | 12 | SPI Flash-SCK/M4 | B2 |
Table 7: MIO - pin assignment of the Quad SPI Flash memory ICs
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The boot source of the Zynq Ultrascale UltraScale MPSoC can be selected via 4 dedicated pins, which generate a 4-bit code to select the boot mode. The pins are accessible on B2B connector J2:
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Following boot modes are possible on the TE0803 Ultrascale UltraScale module by generating the corresponding 4-bit code by the pins 'PS_MODE0' ... 'PS_MODE3' (little-endian alignment):
Boot Mode | Mode Pins [3:0] | MIO Location | Description |
---|---|---|---|
JTAG | 0x0 | JTAG | Dedicated PS interface. |
QSPI32 | 0x2 | MIO[12:0] | Configured on module with dual QSPI Flash Memory. 32-bit addressing. |
SD0 | 0x3 | MIO[25:13] | Supports SD 2.0. |
SD1 | 0x5 | MIO[51:38] | Supports SD 2.0. |
eMMC_18 | 0x6 | MIO[22:13] | Supports eMMC 4.5 at 1.8V. |
USB 0 | 0x7 | MIO[52:63] | Supports USB 2.0 and USB 3.0. |
PJTAG_0 | 0x8 | MIO[29:26] | PS JTAG connection 0 option. |
SD1-LS | 0xE | MIO[51:39] | Supports SD 3.0 with a required |
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For Functional details see ug1085 - Zynq ultrascale UltraScale TRM (Boot Modes Section).
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Signal | B2B Connector pin | Function |
---|---|---|
PLL_SCL / PLL_SDA | J2-90 / J2-92 | I²C interface, extern external pull-ups needed for SCL- /SDA - line. I²C address in current configuration: 1110000b |
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The TE0803-01 SoM is equipped with two on-board oscillators to provide the Zynq 's MPSoC's PS configuration bank 503 with reference clock-signals.
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This features allowing highly flexible power management are achieved by establishing Power Domains for power isolation. The Zynq UltrascaleUltraScale+ MPSoC has multiple power domains, whereby each power domain requires its own particular extern DCDC converters.
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Each Power Domain has its own "Enabling"- and "Power Good"-signals. The power rail 'GT_DCDC' is only necessary for variants of the TE0803 module with the Xilinx Zynq UltrascaleUltraScale+ ZU4CG or ZU4EV MPSoC to generate the voltages for the available Xilinx GTH unit.
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There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DCDC DC-DC converters, which power up further DCDC DC-DC converters and the particular on-board voltages:
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The TE0803 SoM meets the recommended criteria to power up the Xilinx Zynq UltrascaleUltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board DCDC DC-DC converters dedicated to the particular Power Domains and powering up the on-board voltages.
The on-board voltages of the TE0803 SoM will be powered-up in order of a determined sequence by activating the above-mentioned power rails and the Enable-Signals of the DCDC DC-DC converters. The on-board voltages will be powered up at three steps.
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Following diagram clarifies the sequence of enabling the three power instances utilizing the DCDC DC-DC converter control signals ('Enable', 'Power-Good'), which will power-up in descending order as listed in the blocks of the diagram.
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Figure 4: Power-On Sequence Utilizing DCDC DC-DC Converter Control Signals
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The control signals have to be asserted on the B2B connector J2, whereby some of the Power-Good-Signals need extern external pull-up resistors.
Enable-Signal | B2B Connector Pin | Max. Voltage | Note | Power-Good-Signal | B2B Connector Pin | Pull-up Resistor | Note | |
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EN_LPD | J2-108 | 6V | TPS82085SIL data sheet | LP_GOOD | J2-106 | 4K7, pulled up to LP_DCDC | - | |
EN_FPD | J2-102 | DCDCIN | NC7S08P5X data sheet | PG_FPD | J2-110 | 4K7, pulled up to DCDCIN | - | |
EN_PL | J2-101 | max PL_DCIN | left floating for logic high (drive to GND for logic low) | PG_PL | J2-104 | extern external pull-up needed (max. voltage 'GT_DCDC'), max. sink current 1 mA | TPS82085SIL / | |
EN_DDR | J2-112 | DCDCIN | NC7S08P5X data sheet | PG_DDR | J2-114 | 4K7, pulled up to DCDCIN | - | |
EN_PSGT | J2-84 | DCDCIN | NC7S08P5X data sheet | PG_PSGT | J2-82 | extern external pull-up needed (max. 5.5V), max. sink current 1 mA | TPS74801 data sheet | |
EN_GT_R | J2-95 | GT_DCDC | NC7S08P5X data sheet | PG_GT_R | J2-91 | extern external pull-up needed (max. 5.5V), max. sink current 1 mA | TPS74401 data sheet | |
- | - | - | - | PG_VCU_1V0 | J2-97 | extern external pull-up needed (max. 5.5V), | TPS82085SIL data sheet |
Table 16: Recommended operation conditions of DCDC DC-DC converter control signals
Warning |
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To avoid any demages damage to the MPSoC module, check for stabilized on-board voltages in steady state before powering up the MPSoC's I/O bank voltages VCCOx. All I/O's should be tri-stated during power-on sequence. |
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Module Variant | Zynq UltrascaleUltraScale+ Module | Video Codec Unit | GTH Transceiver Unit | Zynq Ultrascale+ Module Junction Temperature | Operating Temperature Range | Transceivers |
---|---|---|---|---|---|---|
TE0803-TE0803-01-02CG-1E | XCZU2CG-1SFVC784E- | - | 0°C- | 100°Cextended|||
TE0803-01-03CG-1E | XCZU3CG-1SFVC784E | - | - | 0°C - 100°C | extended | |
TE0803-01-04CG-1E 1) | XCZU4CG-1SFVC784E | - | yes | 0°C - 100°C | extended | |
TE0803-01-02EG-1E | XCZU2EG-1SFVC784E- | - | 0°C - 100°C | extended | ||
TE0803-01-03EG-1E | XCZU3EG-1SFVC784E | - | - | 0°C - 100°C | extended | |
TE0803-01-04EV-1E 1) | XCZU4EV-1SFVC784E | yes | yes | 0°C - 100°C | extended |
Table 19: Differences between variants of Module module TE0803-01 variants
1) Not yet available
All variants are rated for Extended temperature range (0 - 100 °C).
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Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
Extended grade: 0°C to +85°C100°C.
The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
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Date | Revision | Contributors | Description | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|
| Jan Kumann | New smaller images Temperature information changes. Few corrections.
| |||||||||
| V.4
| Ali Naseri | Current TRM release | ||||||||
2017-05-10 | v.1 | Ali Naseri | Initial document |
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