Page History

224¹⁾

4 GTH lanes

(4 RX / 4TX)

B224_RX3_P, B224_RX3_N, pins J1-51, J1-53
B224_TX3_P, B224_TX3_N, pins J1-50, J1-52

B224_RX2_P, B224_RX2_N, pins J1-57, J1-59
B224_TX2_P, B224_TX2_N, pins J1-56, J1-58

B224_RX1_P, B224_RX1_N, pins J1-63, J1-65
B224_TX1_P, B224_TX1_N, pins J1-62, J1-64

B224_RX0_P, B224_RX0_N, pins J1-69, J1-71
B224_TX0_P, B224_TX0_N, pins J1-68, J1-70

1 reference clock signal (B224_CLK0) from B2B connector
J3 (pins J3-59/J3-61) to bank's pins Y6/Y5

1 reference clock signal (B224_CLK1) from programmable
PLL clock generator U5 to bank's pins V6/V5

4 GTR lanes

(4 RX / 4TX)

B505_RX3_P, B505_RX3_N, pins J2-51, J2-49
B505_TX3_P, B505_TX3_N, pins J2-54, J2-52

B505_RX2_P, B505_RX2_N, pins J2-57, J2-55
B505_TX2_P, B505_TX2_N, pins J2-60, J2-58

B505_RX1_P, B505_RX1_N, pins J2-63, J2-61
B505_TX1_P, B505_TX1_N, pins J2-66, J2-64

B505_RX0_P, B505_RX0_N, pins J2-69, J2-67
B505_TX0_P, B505_TX0_N, pins J2-72, J2-70

2 reference clock signals (B505_CLK0, B505_CLK1) from B2B connector
J2 (pins J2-16/J2-18, J2-10/J2-12) to bank's pins F23/F24, E21/E22

2 reference clock signals (B505_CLK2, B505_CLK3) from programmable
PLL clock generator U5 to bank's pins C21/C22, A21/A22