Page History

Custom_table_size_100

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Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"

Template Change history:

Version	Changes	Author
4.2	Changes Xilinx to AMD	ED
4.1	Minor changes Notes Tables	ED
4.0	Rework for smaller TRM which can be generated faster Reduce Signal Interfaces Pin Reduce On Board Perihery Reduce Power Move Configuration Signals from Overview to own section	JH
3.12	Version History changed from list to table all changed title-alignment for tables from left to center	ma
3.11	update "Recommended Operating Conditions" section
3.1	New general notes for temperature range to "Recommended Operating Conditions"
3.02	add again fix table of content with workaround to use it for pdf and wiki Export Link for key features examples Notes for different Types (with and without Main FPGA) Export Link for Signals, Interfaces and Pins examples Notes for different Types (Modul, Modul Hypride, Evalboard, Carrier)
3.01	remove fix table of content and page layout ( split page layout make trouble with pdf export) changed and add note to signal and interfaces, to on board periphery section ...(not finished)
3.00	→ separation of Carrier/Module and evaluation kit TRM
2.15	add excerpt macro to key features
2.14	add fix table of content add table size as macro

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Important General Note:

If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template:

Scroll Title

anchor	Figure_anchorname
title-alignment	center
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables

Scroll Title

anchor	Table_tablename
title-alignment	center
title	Text

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Example	Comment
1	2

The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
- <type>_<main section>_<name>
  - type: Figure, Table
  - main section:
    - "OV" for Overview
    - "SIP" for Signal Interfaces and Pins,
    - "OBP" for On board Peripherals,
    - "PWR" for Power and Power-On Sequence,
    - "B2B" for Board to Board Connector,
    - "TS" for Technical Specification
    - "VCP" for Variants Currently in Production
    - "RH" for Revision History
  - name: custom, some fix names, see below
- Fix names:
  - "Figure_OV_BD" for Block Diagram
  - "Figure_OV_MC" for Main Components
  - "Table_OV_IDS" for Initial Delivery State
  - "Table_PWR_PC" for Power Consumption
  - "Figure_PWR_PD" for Power Distribution
  - "Figure_PWR_PS" for Power Sequence
  - "Figure_PWR_PM" for Power Monitoring
  - "Table_PWR_PR" for Power Rails
  - "Table_PWR_BV" for Bank Voltages
  - "Table_TS_AMR" for Absolute_Maximum_Ratings
  - "Table_TS_ROC" for Recommended_Operating_Conditions
  - "Figure_TS_PD" for Physical_Dimensions
  - "Table_VCP_SO" for TE_Shop_Overview
  - "Table_RH_HRH" for Hardware_Revision_History
  - "Figure_RH_HRN" for Hardware_Revision_Number
  - "Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>

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-----------------------------------------------------------------------

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Note for Download Link of the Scroll ignore macro:

Link to the base folder of the module (remove de/ or en/ from the URL):
Example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5_Carriers/TE0728/

Scroll Ignore
Download PDF version of this document.

Overview

The Trenz Electronic TE0803 is an industrial grade MPSoC SOM integrating an AMD Zynq UltraScale+, DDR4 SDRAM with 64-Bit width data bus connection, SPI Boot Flash memory for configuration and operation, transceivers (SoC/Variant-dependent) and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking connections in a compact 5.2 cm x 7.6 cm form factor.

Refer to http://trenz.org/te0803-info for the current online version of this manual and other available documentation.

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Notes :

short description of the PCB
Short Link of the wiki resources reference:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0728-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Key Features

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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

→ See examples fro different types <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-KeyFeatures

Excerpt

SoC
- Device: ZU1 / ZU2 / ZU3 / ZU4 / ZU5 ¹⁾
- Engine: CG / EG / EV ¹⁾
- Speedgrade: -1 / -1L / -2 / -2L / -3 ¹⁾
- Temperature Range: Extended / Industrial ¹⁾
- Package: SFVC784
RAM/Storage
- 4 GByte DDR4 SDRAM ^{2) 3)}
- 2 x 64 MByte Serial Flash ³⁾
- EEPROM with MAC address
On Board
- Clock Generator
- Oscillator
Interface
- 4 x B2B Connector (ST5)
  - up to 204 PL IO
    - HP: 156
    - HD: 0 / 48 ³⁾
  - up to 65 PS MIO
  - 4 GTR
  - 4 GTH (with ZU3T, ZU4 and higher)
  - I2C, JTAG, CONFIG
Power
- 3.3 V power supply via B2B Connector needed ⁵⁾.
Dimension
- 76 mm x 52 mm
Notes
¹⁾ Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design.
²⁾ Up to 8 GByte are possible with a maximum bandwidth of 2400 MBit/s.
³⁾ Please, take care of the possible assembly options.
⁵⁾ Dependent on the assembly option a higher input voltage may be possible.

Block Diagram

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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.

Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

Note

Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name.

Example: TE0812 Block Diagram

Note

All created DrawIOs should be named according to the Module name:

Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD

Scroll Title

anchor	Figure_OV_BD
title-alignment	center
title	TE0808 block diagram

Scroll Ignore

draw.io Diagram

border	true

diagramName	TE0803_OV_BD
simpleViewer	false
width
links	auto
tbstyle	top
lbox	true
diagramWidth	541
height	541
revision	1

Scroll Only

Main Components

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Notes :

Picture of the PCB (top and bottom side) with labels of important components
Add List below

Note
For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .

Scroll Title

anchor	Figure_OV_MC
title-alignment	center
title	TE0803 main components

Scroll Ignore

draw.io Diagram

border	true

diagramName	Figure_OV_MC
simpleViewer	false
width
links	auto
tbstyle	top
lbox	true
diagramWidth	760
height	1050
revision	5

Scroll Only

SoC, U1
DDR4, U2, U3, U9, U12
Quad SPI Flash, U7, U17
Connector, J1, J2, J3, J4
EEPROM, U28
Clock Generator, U5
Oscillator, U6, U32
Done LED D1

Initial Delivery State

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Note

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

Scroll Title

anchor	Table_OV_IDS
title-alignment	center
title	Initial delivery state of programmable devices on the module

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Storage device name	Content	Notes
Quad SPI Flash	not programmed
EEPROM	not programmed besides factory programmed MAC address
DDR4 SDRAM	not programmed
Programmable Clock Generator	not programmed

Signals, Interfaces and Pins

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For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins

Note
Table with all connectors and Designtor List of different interfaces per connector IO CNT (for FPGA IOs where functionality can be changed by customer)

Connectors

Scroll Title

anchor	Table_SIP_C
title-alignment	center
title	Board Connectors

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
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sortEnabled	false
cellHighlighting	true

Connector Type	Designator	Interface	IO CNT	Notes
B2B	JM1	MGT PL	up to 4 x MGT (RX/TX)	Assembly option dependent.
B2B	JM1	HP	52 SE / 24 DIFF
B2B	JM2	MGT PS	2 x MGT CLK
B2B	JM2	CLK	2 x DIFF CLK	PLL, 1 x Input, 1 x Output
B2B	JM2	MGT PS	4 x MGT (RX/TX)
B2B	JM2	CFG¹⁾	1x JTAG
B2B	JM2	CFG¹⁾	4x MODE
B2B	JM2	CFG¹⁾	1 x I2C	PLL, EEPROM
B2B	JM2	CFG¹⁾	29 CTRL/Status
B2B	JM3	HD	up to 48 SE / 24 DIFF	Assembly option dependent.
B2B	JM3	MGT PL	MGT CLK
B2B	JM3	MIO	65 GPIO
B2B	JM4	HP	104 SE / 48 DIFF

1) see Configuration and System Control Signals

Test Points

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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test Point	Signal	Notes¹⁾
TP1	PWR_PL_OK

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Scroll Title

anchor	Table_SIP_TPs
title-alignment	center
title	Test Points Information

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
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sortEnabled	false
cellHighlighting	true

Test Point	Signal	Notes¹⁾
TP1	PLL_SCL	pulled-up to PS_1V8
TP2	PLL_SDA	pulled-up to PS_1V8
TP3	GND
TP4	GND
TP5	GND
TP6	PL_1V8
TP7	GND
TP8	GND
TP9	PL_VCCINT_IO
TP10	GND
TP11	PL_VCCINT
TP12	PL_VCU_0V9
TP13	FP_0V85
TP14	PS_1V8
TP15	GND
TP16	DDR_2V5
TP17	DDR_PLL
TP18	DDR_1V2
TP20	MGTAVTT
TP21	VTT
TP22	PL_GT_1V05
TP23	VREFA
TP24	MGTVCCAUX
TP25	MGTAVCC
TP27	PS_PLL
TP28	PS_AVTT
TP29	LP_0V85
TP30	PS_AUX
TP31	PS_AVCC
TP32	PS_CLK
TP34	POR_B	pulled-up to PS_1V8

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

On-board Peripherals

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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example:

Chip/Interface	Designator	Connected To	Notes
ETH PHY	U10	B2B connector J1 SoC MIO	Gigabit ETH PHY

Scroll Title

anchor	Table_OBP
title-alignment	center
title	On board peripherals

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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sortByColumn	1
sortEnabled	false
cellHighlighting	true

Chip/Interface	Designator	Connected To	Notes
DDR4 SDRAM	U2, U3, U9, U12	SoC - PS
Quad SPI Flash	U7, U17	SoC - PS	Booting.
EEPROM	U28	B2B - J2
Clock Generator	U5	B2B - J2 SoC -MGT
Oscillator	U6	Clock Generator	25 MHz
Oscillator	U32	SoC	33.333333 MHz

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For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

Configuration and System Control Signals

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Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)

Scroll Title

anchor	Table_OV_CNTRL
title-alignment	center
title	Controller signal.

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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sortByColumn	1
sortEnabled	false
cellHighlighting	true

Connector+Pin	Signal Name	Direction¹⁾	Description
J2-82	PG_PSGT	OUT	GTR transceivers powered-up.
J2-83	MR	IN	Manual reset.
J2-84	EN_PSGT	IN	Enable GTR transceiver power-up.
J2-86	ERR_STATUS	OUT	PS error status ²⁾.
J2-88	ERR_OUT	OUT	PS error indication ²⁾.
J2-90	PLL_SCL	IN	I2C clock. Pulled up to PS_1V8.
J2-91	PG_GT_R	OUT	Right GTH Transceivers powered-up.
J2-92	PLL_SDA	IN/OUT	I2C data. Pulled up to PS_1V8.
J2-95	EN_GT_R	IN	Enable right GTH transceiver power-up.
J2-96	SRST_B	IN	System reset ²⁾. Pulled-up to PS_1V8.
J2-97	PG_VCU	OUT	VCU powered-up.
J2-98	INIT_B	IN/OUT	Initialization completion indicator after POR ²⁾. Pulled-up to PS_1V8.
J2-100	PROG_B	IN/OUT	Power-on reset ²⁾. Pulled-up to PS_1V8.
J2-101	EN_PL	IN	Enable programable logic power-up.
J2-102	EN_FPD	IN	Enable full-power domain power-up.
J2-103 / J2-105 / J2-107 / J2-109	MODE3..0	IN	Boot mode selection ²⁾: JTAG QUAD-SPI (32 Bit) SD1 (2.0) eMMC (1.8 V) SD1 LS (3.0) Supported Modes depends also on used Carrier.
J2-104	PG_PL	OUT	Programmable logic powered-up. Pulled-up to PL_DCIN.
J2-106	LP_GOOD	OUT	Low-power domain powered-up. Pulled up to LP_DCDC.
J2-108	EN_LPD	IN	Enable low-power domain power-up.
J2-110	PG_FPD	OUT	Full-power domain powered-up. Pulled-up to DCDCIN.
J2-112	EN_DDR	IN	Enable DDR power-up.
J2-114	PG_DDR	OUT	DDR power supply powered-up. Pulled-up to DCDCIN.
J2-116	DONE	OUT	PS done signal ²⁾. Pulled-up to PS_1V8.
J2-119 / J2-121	DX_P / DX_N	-	SoC temperatur sensing diode pins ²⁾.
J2-120 / J2-122 / J2-124 / J2-126	TCK / TDI / TDO / TMS	Signal-dependent	JTAG configuration and debugging interface. JTAG reference voltage: PS_1V8
J2-125	PSBATT	IN	PS RTC Battery supply voltage ^{2) 3)}.
J2-127	PUDC_B	IN	Configuration pull-ups setting ²⁾. Pulled-up to PL_1V8.

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

²⁾ See UG1085 for additional information.

Power and Power-On Sequence

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Enter the default value for power supply and startup of the module here.

Order of power provided Voltages and Reset/Enable signals

Link to Schematics, for power images or more details

Power Rails

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List of all Powerrails which are accessible by the customer

Main Power Rails and Variable Bank Power

Scroll Title

anchor	Table_PWR_PR
title-alignment	center
title	Module power rails.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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sortByColumn	1
sortEnabled	false
cellHighlighting	true

Power Rail Name/ Schematic Name	Connector + Pin	Direction¹⁾
VCCO_66	J1-90 / J1-120	IN
VREF_66	J1-108	IN
PL_1V8	J1-91 / J1-121	OUT
PL_DCIN	J1-151 / J1-153 / J1-155 / J1-157 / J1-159	IN
LP_DCDC	J2-138 / J2-140 / J2-142 / J2-144	IN
DCDCIN	J2-153 / J2-154 / J2-155 / J2-156 / J2-157 / J2-158 / J2-159 / J2-160	IN
PS_1V8	J2-99 / J3-147 / J3-148	OUT
PS_BATT	J2-125	IN
DDR_1V2	J2-135	OUT
VCCO_25	J3-15 / J3-16	IN
VCCO_26	J3-43 / J3-44	IN
GT_DCDC	J3-157 / J3-158 / J3-159 / J3-160	IN
VCCO_64	J4-58 / J4-106	IN
VREF_64	J4-88	IN
VCCO_65	J4-69 / J4-105	IN
VREF_65	J4-15	IN

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Recommended Power up Sequencing

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List baseboard design hints for final baseboard development.

Scroll Title

anchor	Table_BB_DH
title-alignment	center
title	Baseboard Design Hints

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
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cellHighlighting	true

Sequence	Net name	Recommended Voltage Range	Pull-up/down	Description	Notes
0	-	-	-	Configuration signal setup.	See Configuration and System Control Signals.
1 ¹⁾	PSBATT	1.2 V ... 1.5 V	-	Battery connection.	Battery Power Domain usage. When not used, tie to GND.
2	Processing System (PS):			Procedure for PS starting.
2.1	Low-power domain:			Bring-up for low-power domain PS.
2.1.1	LP_DCDC	3.3 V (± 5 %) ²⁾	-	Low-power domain power supply.	Main module power supply for low-power domain. 5.5 A recommended. Power consumption depends mainly on design and cooling solution.
2.1.2	EN_LPD	-	-	Low-power domain power enable.
2.1.3	LP_GOOD	-	PU ³⁾, LP_DCDC	Low-power domain power good status.	Module power-on sequencing for low-power domain finished.
2.2	Full-power domain:			Bring-up for full-power domain PS.	Full-power PS domain needs powered low-power PS domain.
2.2.1	DCDCIN	3.3 V (± 5 %) ²⁾		Full-power domain and GTR transceiver power supply.	Main module power supply for full-power domain. 7 A recommended. Power consumption depends mainly on design and cooling solution.
2.2.2	EN_FPD	DCDCIN	-	Full-power domain power enable.
2.2.3	PG_FPD	-	PU ³⁾, DCDCIN	Full-power domain power good status.	Module power-on sequencing for full-power domain finished.
2.2.4	EN_DDR	DCDCIN	-	DDR memory power enable.
2.2.5	PG_DDR	-	PU ³⁾, DCDCIN	DDR memory power good status.	Module power-on sequencing for DDR memory finished.
2.3	GTR Transceiver			Procedure for GTR transceiver starting.	PS transceiver usage needs powered PS (low- and full-power domain).
2.3.1	EN_PSGT	DCDCIN	-	GTR transceiver power enable.
2.3.2	PG_PSGT	-	-	GTR transceiver power good status.	Module power-on sequencing for GTR transceiver finished.
2	Programmable Logic (PL)			Procedure for PL starting.	PL usage needs powered PS low-power domain.
2.1	PL_DCIN	3.3 V (± 5 %) ²⁾	-	Programmable logic power supply.	Main module power supply for programmable logic. 12 A recommended. Power consumption depends mainly on design and cooling solution.
2.2	EN_PL	-	PU ³⁾, PL_DCIN	Programmable logic power enable.
2.3	PG_PL	-	PU ³⁾, PL_DCIN	Programmable logic power good status.	Module power-on sequencing for programmable logic finished. Periphery and variable bank voltages can be enabled on carrier.
2.4	PG_VCU	-	PU ³⁾, PL_DCIN	Video codec unit power good status.	Assembly variant dependent.
2.5	VCCO_25 / VCCO_26 / VCCO_64 / VCCO_65 / VCCO_66	⁴⁾	-	Module bank voltages.	Enable bank voltages after PG_PL deassertion.
3	GTH / GTY Transceiver			Procedure for GTH / GTY transceiver starting.	PL transceiver usage needs powered PL and low-power PS domain.
3.1	GT_DCDC	3.3 V (± 5 %) ²⁾	-	GTH transceiver power supply.	Main module power supply for GTH transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution.
3.2	EN_GT_R	GT_DCDC	-	GTH right transceiver power enable.
3.3	PG_GT_R	-	-	GTH transceiver power good status.
4	MR			Manual Reset	Low active release after all needed power domains are enabled.

¹⁾ Optional

²⁾ Dependent on the assembly option a higher input voltage may be possible.

³⁾ On module

⁴⁾ See DS925 for additional information.

Board to Board Connectors

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This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series,
For example: 6 x 6 SoM LSHM B2B Connectors
Include Page
6 x 6 SoM LSHM B2B Connectors
6 x 6 SoM LSHM B2B Connectors

Include Page

	5.2 x 7.6 UltraSoM+ ST5 and SS5 B2B Connectors
	5.2 x 7.6 UltraSoM+ ST5 and SS5 B2B Connectors

Technical Specifications

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List of all Powerrails which are accessible by the customer

Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)

Absolute Maximum Ratings ^*)

Scroll Title

anchor	Table_TS_AMR
title-alignment	center
title	Absolute maximum ratings

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Power Rail Name/ Schematic Name	Description	Min	Max	Unit
LP_DCDC	Micromodule Power	-0.300	4.0	V
DCDCIN	Micromodule Power	-0.300	6.5	V
GT_DCDC	Micromodule Power	-0.300	6.0	V
PL_DCIN	Micromodule Power	-0.300	4.0	V
PS_BATT	RTC / BBRAM	-0.500	2.000	V
VCCO_25	HD IO Bank power supply	-0.500	3.400	V
VCCO_26	HD IO Bank power supply	-0.500	3.400	V
VCCO_64	HP IO Bank power supply	-0.500	2.000	V
VCCO_65	HP IO Bank power supply	-0.500	2.000	V
VCCO_66	HP IO Bank power supply	-0.500	2.000	V
VREF_64	Bank input reference voltage	-0.500	2.000	V
VREF_65	Bank input reference voltage	-0.500	2.000	V
VREF_66	Bank input reference voltage	-0.500	2.000	V

^*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Variants of modules are described here: Article Number Information
Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.

Scroll Title

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title-alignment	center
title	Recommended operating conditions.

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Parameter	Min	Max	Units	Reference Document
LP_DCDC ¹⁾	3.135	3.465	V
DCDCIN ¹⁾	3.135	3.465	V
GT_DCDC ¹⁾	3.135	3.465	V
PL_DCIN ¹⁾	3.135	3.465	V
PS_BATT	1.200	1.500	V	See FPGA datasheet.
VCCO_25	1.140	3.400	V	See FPGA datasheet.
VCCO_26	1.140	3.400	V	See FPGA datasheet.
VCCO_64	0.950	1.900	V	See FPGA datasheet.
VCCO_65	0.950	1.900	V	See FPGA datasheet.
VCCO_66	0.950	1.900	V	See FPGA datasheet.
VREF_64	0.6	1.2	V	See FPGA datasheet.
VREF_65	0.6	1.2	V	See FPGA datasheet.
VREF_66	0.6	1.2	V	See FPGA datasheet.

¹⁾ Higher values may possible. For more information consult schematic and according datasheets.

Physical Dimensions

Module size: 76 mm × 52 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 5 mm.

PCB thickness: 1.740 mm (± 10 %).

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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

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draw.io Diagram

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Currently Offered Variants

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Set correct link to the shop page overview table of the product on English and German.

Example for TE0706:

ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

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title	Trenz Electronic Shop Overview

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Trenz shop TE0803 overview page
English page	German page

Revision History

Hardware Revision History

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Set correct links to download Carrier, e.g. TE0706 REV02:

TE0706-02 -> https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

Date format: YYYY-MM-DD
Example:
Date Revision Changes Documentation Link
2020-11-25 REV02
Resistors R14 and R15 was replaced by 953R (was 5K1)
Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
REV02

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anchor	Figure_RV_HRN
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title	Board hardware revision number.

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Date	Revision	Changes	Documentation Link
2020-12-15	04	Revised PL_VCCINT power supply. EN63A0QI replaced by TPS548A28RWWR. PCB: revised routing and components placement; Added support of wide SDRAM DDR4 packages. PCB: revised routing and components placement; Added option to select POR_OVERRIDE level (R12 and R93) VCCO pins for unused Bank 44 connected together. Same for unused Bank 24 (UG583 recomendation) PCB: updated signal trace lengths. PCB: updated silkscreen. Added company address, CE and WEEE symbols; PCB: added module orientation rectangle pointer Changed resistor values of R29, R31, R35, R39, R44-R47 (BOM optimization) Removed traceability part (Obsolete component) Changed capacitor C92 for all variants from 100 nF to 1 nF. U4 can be either TPS548A28RWWR or MPQ8633BGLE-Z which is up to Trenz Electronic GmbH.	TE0803-04
2019-03-18	03	Added support of DDP DDR4 Added support of Low power FPGA (-L1/L2). Revised testpoints Revised J1-J4 connectors net label style	TE0803-03
2018-07-19	02	Added LDO to DDR_PLL All differential pairs length matched with tollerance 0.1mm (excluding package delays) Added MAC EEPROM U28 VPS_MGTRAVCC set to 0.85V Added pull-up resistors R68, R69	TE0803-02
2016-12-23	01	First production release	TE0803-01

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

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Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
- Metadata is only used of compatibility of older exports

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Date

Revision

Contributor

Description

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Review and publishing

2023-10-06

v.52

ED

Updated to new TRM style
Updated for REV04

2022-05-19

v.51

ED

Added note regarding DCDC U4.

2022-02-25

v.50

John Hartfiel

Add Note to PLL

2022-02-08

v.46

John Hartfiel

Correction on Power section
Correction GTH Clock connection

2021-05-17

v.41

John Hartfiel

typo correction in DDR section

2021-03-11

v.40

John Hartfiel

typo
fixed MGT Lanes RX/TX order

2019-07-15

v.36

John Hartfiel

correction SPLL section

2019-07-02

v.35

John Hartfiel

add eeprom section
update PCB Revision section

2019-06-19

v.33

John Hartfiel

update links
correction flash section

2018-08-20

v.29

John Hartfiel

power section: add missing PS_1V8 output pin

2018-08-06

v.28

John Hartfiel

typo correction

2017-11-13

v.23

Ali Naseri

updated B2B connector max. current rating per pin

2017-11-13

v.19

John Hartfiel

rework B2B section

2017-10-19

v.18

John Hartfiel

Removed ES1 Note

2017-08-15

v.17

Vitali Tsiukala

Changed Signals Count in the table B2B-connectors

2017-08-07

v.14

Jan Kumann

New smaller images.
New QSPI Flash MIO mapping table.
Temperature information changes.
Few corrections.

2017-05-17

V.4

Ali Naseri

Current TRM release.

2017-05-10

v.1

Ali Naseri

Initial document.

--

all

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--

Disclaimer

Include Page

	IN:Legal Notices
	IN:Legal Notices

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Trenz Electronic Documentation

Versions Compared

Old Version 54

New Version 55

Key

Overview

Key Features

Block Diagram

Main Components

Initial Delivery State

Signals, Interfaces and Pins

Connectors

Test Points

On-board Peripherals

DDR4 SDRAM

Quad SPI Flash

EEPROM

Clock Generator

Oscillator

Configuration and System Control Signals

Power and Power-On Sequence

Power Rails

Recommended Power up Sequencing

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings ^*)

Recommended Operating Conditions

Physical Dimensions

Currently Offered Variants

Revision History

Hardware Revision History

Document Change History

Disclaimer

Table of contents

Trenz Electronic Documentation

Page History

Versions Compared

Old Version 54

New Version 55

Key

Overview

Key Features

Block Diagram

Main Components

Initial Delivery State

Signals, Interfaces and Pins

Connectors

Test Points

On-board Peripherals

DDR4 SDRAM

Quad SPI Flash

EEPROM

Clock Generator

Oscillator

Configuration and System Control Signals

Power and Power-On Sequence

Power Rails

Recommended Power up Sequencing

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings *)

Recommended Operating Conditions

Physical Dimensions

Currently Offered Variants

Revision History

Hardware Revision History

Document Change History

Disclaimer

Table of contents

Absolute Maximum Ratings ^*)