Page History
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| Bank | Type | B2B Connector | Count of MGT Lanes | Schematic Names / Connector Pins | MGT Bank's Reference Clock Inputs |
|---|---|---|---|---|---|
2241)
| GTH | J1 | 4 GTH lanes (4 RX / 4TX) | B224_RX3_P, B224_RX3_N, pins J1-51, J1-53 B224_RX2_P, B224_RX2_N, pins J1-57, J1-59 B224_RX1_P, B224_RX1_N, pins J1-63, J1-65 B224_RX0_P, B224_RX0_N, pins J1-69, J1-71 | 1 reference clock signal (B224_CLK0) from B2B connector 1 reference clock signal (B224_CLK1) from programmable |
| 505 | GTR | J2 | 4 GTR lanes (4 RX / 4TX) | B505_RX3_P, B505_RX3_N, pins J2-51, J2-49 B505_RX2_P, B505_RX2_N, pins J2-57, J2-55 B505_RX1_P, B505_RX1_N, pins J2-63, J2-61 B505_RX0_P, B505_RX0_N, pins J2-69, J2-67 | 2 reference clock signals (B505_CLK0, B505_CLK1) from B2B connector 2 reference clock signals (B505_CLK2, B505_CLK3) from programmable |
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Quad SPI Flash memory ICs U7 and U17 are connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO0..MIO5 and MIO7..MIO12.
| MIO | U7 Pin | Pin Name | MIO | U17 Pin | Pin Name | ||
|---|---|---|---|---|---|---|---|
| 0 | B2 | CLK | 7 | C2 | CS# | ||
| 1 | D2 | DO/IO1 | 8 | D3 | DI/IO0 | ||
| 2 | C4 | WP#/IO2 | 9 | D2 | DO/IO1 | ||
| 3 | D4 | HOLD#/IO3 | 10 | C4 | WP#/IO2 | ||
| 4 | D3 | DI/IO0 | 11 | D4 | HOLD#/IO3 | ||
| 5 | C2 | CS# | 12 | B2 | CLK |
Table 7: MIO pin assignment of the Quad SPI Flash memory ICs
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| Enable-Signal | B2B Connector Pin | Max. Voltage | Note | Power-Good-Signal | B2B Connector Pin | Pull-up Resistor | Note | ||
|---|---|---|---|---|---|---|---|---|---|
| EN_LPD | J2-108 | 6V | TPS82085SIL data sheet | LP_GOOD | J2-106 | 4K7, pulled up to LP_DCDC | - | ||
| EN_FPD | J2-102 | DCDCIN | NC7S08P5X data sheet | PG_FPD | J2-110 | 4K7, pulled up to DCDCIN | - | ||
| EN_PL | J2-101 | max PL_DCIN | Left floating for logic high (drive to GND for logic low) | PG_PL | J2-104 | External pull-up needed (max. voltage 'GT_DCDC'), Max. sink current 1 mA | TPS82085SIL / | ||
| EN_DDR | J2-112 | DCDCIN | NC7S08P5X data sheet | PG_DDR | J2-114 | 4K7, pulled up to DCDCIN | - | ||
| EN_PSGT | J2-84 | DCDCIN | NC7S08P5X data sheet | PG_PSGT | J2-82 | External pull-up needed (max. 5.5V), Max. sink current 1 mA | TPS74801 datasheet | ||
| EN_GT_R | J2-95 | GT_DCDC | NC7S08P5X data sheet | PG_GT_R | J2-91 | External pull-up needed (max. 5.5V), Max. sink current 1 mA | TPS74401 datasheet | ||
| - | - | - | - | PG_VCU_1V0 | J2-97 | External pull-up needed (max. 5.5V), | TPS82085SIL datasheet |
Table 16: Recommended operation conditions of DC-DC converter control signals
| Warning |
|---|
| To avoid any damage to the MPSoC module, check for stabilized on-board voltages in steady state before powering up the MPSoC's I/O bank voltages VCCOx. All I/O's should be tri-stated during power-on sequence. |
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Variants Currently In Production
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| Trenz shop TE0803 overview page | |
|---|---|
| English page | German page |
Technical Specifications
Absolute Maximum Ratings
| Parameter | Min | Max | Unit | Notes / |
|---|
Table 19: Differences between module TE0803-01 variants
1) Not yet available
All variants are rated for Extended operating temperature range (0 - 100 °C).
Technical Specifications
Absolute Maximum Ratings
| Parameter | Min | Max | Unit | Notes / Reference Document |
|---|---|---|---|---|
| PL_DCIN | -0.3 | 7 | V | TPS82085SIL / EN63A0QI data sheet |
| DCDCIN | -0.3 | 7 | V | TPS82085SIL / TPS51206PSQ data sheet |
| LP_DCDC | -0.3 | 4 | V | TPS3106K33DBVR data sheet |
| GT_DCDC | -0.3 | 7 | V | TPS82085SIL data sheet |
| PS_BATT | -0.5 | 2 | V | Xilinx DS925 data sheet |
| VCCO for HD I/O banks | -0.5 | 3.4 | V | Xilinx DS925 data sheet |
| VCCO for HP I/O banks | -0.5 | 2 | V | Xilinx DS925 data sheet |
| VREF | -0.5 | 2 | V | Xilinx DS925 data sheet |
| I/O input voltage for HD I/O banks | -0.55 | VCCO + 0.55 | V | Xilinx DS925 data sheet |
| I/O input voltage for HP I/O banks | -0.55 | VCCO + 0.55 | V | Xilinx DS925 data sheet |
| PS I/O input voltage (MIO pins) | -0.5 | VCCO_PSIO + 0.55 | V | Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally |
| Receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage | -0.5 | 1.2 | V | Xilinx DS925 data sheet |
| Voltage on input pins of NC7S08P5X 2-Input AND Gate | -0.5 | VCC + 0.5 | V | NC7S08P5X data sheet, see schematic for VCC |
| Voltage on input pins (nMR) of TPS3106K33DBVR Voltage Monitor, U41 | -0.3 | VDD + 0.3 | V | TPS3106 data sheet, VDD = LP_DCDC |
| "Enable"-signals on TPS82085SIL ('EN_LPD') | -0.3 | 7 | V | TPS82085SIL data sheet |
| Storage temperature (ambient) | -40 | 100 | °C | ROHM Semiconductor SML-P11 Series data sheet |
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| Date | Revision | Contributors | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| Ali Naseri |
| |||||||||
2017-11-13 | v.19 | John Hartfiel |
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| 2017-10-19 | v.18 | John Hartfiel |
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| 2017-08-15 | v.17 | Vitali Tsiukala |
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2017-08-07 | v.14 | Jan Kumann |
| ||||||||
2017-05-17 | V.4 | Ali Naseri | Current TRM release. | ||||||||
| 2017-05-10 | v.1 | Ali Naseri | Initial document. |
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