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- Xilinx ZYNQ UltraScale+ MPSoC, U1
- 2-Input AND Gate, U39
- Red LED (DONE), D1
- 256Mx16 DDR4-2400 SDRAM, U12
- 256Mx16 DDR4-2400 SDRAM, U9
- 256Mx16 DDR4-2400 SDRAM, U2
- 256Mx16 DDR4-2400 SDRAM, U3
- 12A PowerSoC DC-DC converter, U4 (either TPS548A28RWWR or MPQ8633BGLE-Z is assembled which is up to Trenz Electronic GmbH)
- 1.5A LDO DC-DC converter, U10
- 1.5A LDO DC-DC converter, U8
- Voltage monitor circuit, U41
- 0.35A LDO DC-DC converter, U26
- 0.35A LDO DC-DC converter, U27
- Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
- Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
- Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
- Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
- 4-channel programmable PLL clock generator, U5
- Low-power programmable oscillator @ 25.000000 MHz, U5
- Low-power programmable oscillator @ 33.333333 MHz (PS_CLK), U32
- 256 Mbit serial NOR Flash memory, U7
- 256 Mbit serial NOR Flash memory, U17
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Table 8: Boot mode pins on B2B connector J2
Following boot modes are possible on the TE0803 UltraScale+ MPSoC module by generating the corresponding 4-bit code with pins 'PS_MODE0' ... 'PS_MODE3' (little-endian alignment):
Boot Mode | Mode Pins [3:0] | MIO Location | Description |
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JTAG | 0x0 | JTAG | Dedicated PS interface. |
QSPI32 | 0x2 | MIO[12:0] | Configured on module with dual QSPI Flash Memory. 32-bit addressing. Supports single and dual parallel configurations. Stack and dual stack is not supported. |
SD0 | 0x3 | MIO[25:13] | Supports SD 2.0. |
SD1 | 0x5 | MIO[51:38] | Supports SD 2.0. |
eMMC_18 | 0x6 | MIO[22:13] | Supports eMMC 4.5 at 1.8V. |
USB 0 | 0x7 | MIO[52:63] | Supports USB 2.0 and USB 3.0. |
PJTAG_0 | 0x8 | MIO[29:26] | PS JTAG connection 0 option. |
SD1-LS | 0xE | MIO[51:39] | Supports SD 3.0 with a required SD 3.0 compliant level shifter. |
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Figure 3: Power Distribution Diagram (For U4 either TPS548A28RWWR or MPQ8633BGLE-Z is assembled which is up to Trenz Electronic GmbH)
Note |
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Current rating of Samtec Razor Beam LP Terminal/Socket Strip ST5/SS5 B2B connectors is 1.5 A per pin (1 pin powered per row). |
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Date | Revision | Contributors | Description |
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Page info |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| Page info |
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infoType | Current version |
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dateFormat | yyyy-MM-dd |
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prefix | v. |
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type | Flat |
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| Page info |
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infoType | Modified by |
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type | Flat |
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| - Added note regarding DCDC U4.
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22-02-25 | v.50 | John Hartfiel | |
22-02-08 | v.46 | John Hartfiel | - Correction on Power section
- Correction GTH Clock connection
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2021-05-17 | v.41 | John Hartfiel | - typo correction in DDR section
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2021-03-11 | v.40 | John Hartfiel | - typo
- fixed MGT Lanes RX/TX order
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2019-07-15 | v.36 | John Hartfiel | |
2019-07-02 | v.35 | John Hartfiel | - add eeprom section
- update PCB Revision section
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2019-06-19 | v.33 | John Hartfiel | - update links
- correction flash section
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| v.29 | John Hartfiel | - power section: add missing PS_1V8 output pin
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| v.28 | John Hartfiel | |
2017-11-13 | v.23 | Ali Naseri | - updated B2B connector max. current rating per pin
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| | John Hartfiel | |
2017-10-19 | | John Hartfiel | |
2017-08-15 | v.17 | Vitali Tsiukala | - Changed Signals Count in the table B2B-connectors
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| | Jan Kumann | - New smaller images.
- New QSPI Flash MIO mapping table.
- Temperature information changes.
- Few corrections.
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| | Ali Naseri | Current TRM release. |
2017-05-10 | v.1 | Ali Naseri | Initial document. |
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