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Voltages on B2B Connectors | B2B J1 Pin | B2B J2 Pin | B2B J3 Pin | B2B J4 Pin | Input/ Output | Note |
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PL_DCIN | J1-151, J1-153,J1-155, J1-157, J1-159 | - | - | - | Input | - |
DCDCIN | - | J2-154, J2-156, J2-158, J2-160, J2-153, J2-155, J2-157, J2-159 | - | - | Input | - |
LP_DCDC | - | J2-138, J2-140, J2-142, J2-144 | - | - | Input | - |
PS_BATT | - | J2-125 | - | - | Input | - |
GT_DCDC | - | - | J3-157, J3-158, J3-159, J3-160 | - | Input | - |
PS_1V8 | - | J2-99 | J3-147, J3-148 | - | Output | Internal voltage level 1.8V nominal output |
PL_1V8 | J1-91, J1-121 | - | - | - | Output | Internal voltage level 1.8V nominal output |
DDR_1V2 | - | J2-135 | - | - | Output | Internal voltage level 1.2V nominal output |
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Parameter | Min | Max | Unit | Notes / Reference Document |
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PL_DCIN | -0.3 | 74 | V | TPS82085SIL / EN63A0QI data sheet |
DCDCIN | -0.3 | 74 | V | TPS3106K33DBVR / TPS82085SIL / TPS51206PSQ data sheet |
LP_DCDC | -0.3 | 4 | V | TPS3106K33DBVR data sheet |
GT_DCDC | -0.3 | 74 | V | TPS82085SIL data sheet |
PS_BATT | -0.5 | 2 | V | Xilinx DS925 data sheet |
VCCO for HD I/O banks | -0.5 | 3.4 | V | Xilinx DS925 data sheet |
VCCO for HP I/O banks | -0.5 | 2 | V | Xilinx DS925 data sheet |
VREF | -0.5 | 2 | V | Xilinx DS925 data sheet |
I/O input voltage for HD I/O banks | -0.55 | VCCO + 0.55 | V | Xilinx DS925 data sheet |
I/O input voltage for HP I/O banks | -0.55 | VCCO + 0.55 | V | Xilinx DS925 data sheet |
PS I/O input voltage (MIO pins) | -0.5 | VCCO_PSIO + 0.55 | V | Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally |
Receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage | -0.5 | 1.2 | V | Xilinx DS925 data sheet |
Voltage on input pins of NC7S08P5X 2-Input AND Gate | -0.5 | VCC + 0.5 | V | NC7S08P5X data sheet, see schematic for VCC |
Voltage on input pins (nMR) of TPS3106K33DBVR Voltage Monitor, U41 | -0.3 | VDD + 0.3 | V | TPS3106 data sheet, VDD = LP_DCDC |
"Enable"-signals on TPS82085SIL ('EN_LPD') | -0.3 | 7 | V | TPS82085SIL data sheet |
Storage temperature (ambient) | -40 | 100 | °C | ROHM Semiconductor SML-P11 Series data sheet |
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Parameter | Min | Max | Unit | Notes / Reference Document |
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PL_DCIN | 23.53 | 3.6 | V | EN63A0QI / TPS82085SIL data sheet |
DCDCIN | 3.13 | 3.6 | V | TPS82085SIL / TPS51206PSQ data sheet |
LP_DCDC | 23.53 | 3.6 | V | TPS82085SIL / TPS3106K33DBVR data sheet |
GT_DCDC | 2.5 | 3.6 | V | TPS82085SIL data sheet |
PS_BATT | 1.2 | 1.5 | V | Xilinx DS925 data sheet |
VCCO for HD I/O banks | 1.14 | 3.4 | V | Xilinx DS925 data sheet |
VCCO for HP I/O banks | 0.95 | 1.9 | V | Xilinx DS925 data sheet |
I/O input voltage for HD I/O banks. | -0.2 | VCCO + 0.2 | V | Xilinx DS925 data sheet |
I/O input voltage for HP I/O banks | -0.2 | VCCO + 0.2 | V | Xilinx DS925 data sheet |
PS I/O input voltage (MIO pins) | -0.2 | VCCO_PSIO + 0.2 | V | Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally |
Voltage on input pins of NC7S08P5X 2-Input AND Gate | 0 | VCC | V | NC7S08P5X data sheet, see schematic for connected VCCs |
Voltage on input pins (MR) of TPS3106K33DBVR Voltage Monitor, U41 | 0 | VDD | V | TPS3106 data sheet, VDD = LP_DCDC |
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Date | Revision | Contributors | Description | ||||||||||||||||||||||||
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2021-05-17 | v.41 | John Hartfiel |
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2021-03-11 | v.40 | John Hartfiel |
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2019-07-15 | v.36 | John Hartfiel |
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2019-07-02 | v.35 | John Hartfiel |
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2019-06-19 | v.33 | John Hartfiel |
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2018-08-20 | v.29 | John Hartfiel |
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2018-08-06 | v.28 | John Hartfiel |
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2017-11-13 | v.23 | Ali Naseri |
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2017-11-13 | v.19 | John Hartfiel |
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2017-10-19 | v.18 | John Hartfiel |
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2017-08-15 | v.17 | Vitali Tsiukala |
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2017-08-07 | v.14 | Jan Kumann |
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2017-05-17 | V.4 | Ali Naseri | Current TRM release. | ||||||||||||||||||||||||
2017-05-10 | v.1 | Ali Naseri | Initial document. |
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