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- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"
Template Change history: Date | Version | Changes | Author |
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| 4.2 | | ED |
| 4.1 | | ED |
| 4.0 | - Rework for smaller TRM which can be generated faster
- Reduce Signal Interfaces Pin
- Reduce On Board Periphery
- Reduce Power
- Move Configuration Signals from Overview to own section
| JH |
| 3.12 | - Version History
- changed from list to table
- all
- changed title-alignment for tables from left to center
| ma |
| 3.11 | - update "Recommended Operating Conditions" section
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| 3.1 | - New general notes for temperature range to "Recommended Operating Conditions"
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| 3.02 | - add again fix table of content with workaround to use it for pdf and wiki
- Export Link for key features examples
- Notes for different Types (with and without Main FPGA)
- Export Link for Signals, Interfaces and Pins examples
- Notes for different Types (Modul, Modul Hybrid, Evalboard, Carrier)
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| 3.01 | - remove fix table of content and page layout ( split page layout make trouble with pdf export)
- changed and add note to signal and interfaces, to on board periphery section
- ...(not finished)
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| 3.00 | - → separation of Carrier/Module and evaluation kit TRM
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| 2.15 | - add excerpt macro to key features
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| 2.14 | - add fix table of content
- add table size as macro
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Important General Note:
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----------------------------------------------------------------------- |
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Note for Download Link of the Scroll ignore macro: |
Overview
The Trenz Electronic TEG2000 is an industrial-grade FPGA module integrating a CologneChip GateMate A1 FPGA, a 16 MByte QSPI Flash, level shifter, LEDs and several clocking and power components necessary for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at a very competitive price. All Trenz Electronic SoMs in 4 x 5 cm form factor are mechanically compatible.
Refer to http://trenz.org/teg2000-info for the current online version of this manual and other available documentation.
Key Features
Excerpt |
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- SoC/FPGA/Module
- CologneChip GateMate A1 (CCGM1A1)
- performance mode: economy (VDD @ 1.0Vlow power, economy, speed 1)
- Temperature range: industrial (-20°C to 85°C)
- RAM/Storage
- On Board
- Interface
2 x B2B Connector (LSHM) - Configuration via Flash on board, USB or JTAG
- 5 Gb/s SerDes interface
- Diverse I/O- and LVDS configurations:
- 5 banks (SA,EB,WC,EA,WB) with 18 I/Os or 9 LVDS pairs each
- 1 bank (NB) with 12 I/Os or 6 LVDS pairs
- 1 bank (NA) with 14 I/Os or 6 LVDS pairs
- 1 bank (SB) with 6 I/Os @ 1.8V and 8 I/Os level shifted @ 3.3V
- Power
- Dimension
- Notes
- 1) Please, take care of the possible assembly options.
- Other assembly options for cost or performance optimization plus high volume prices available on request.
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Block Diagram
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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.
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Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name. Example: TE0812 Block Diagram |
Note |
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All created DrawIOs should be named according to the Module name: Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD |
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anchor | Figure_OV_BD |
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title-alignment | center |
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title | TEG2000 block diagram |
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draw.io Diagram |
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border | true |
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diagramName | TEG2000_OV_BD |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | top |
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lbox | true |
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diagramWidth | 692 |
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revision | 1 |
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Main Components
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Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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anchor | Figure_OV_MC |
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title-alignment | center |
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title | TEG2000 main components |
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draw.io Diagram |
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border | true |
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diagramName | TEG2000_TRM_MainComp |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | top |
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lbox | true |
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diagramWidth | 642 |
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revision | 1 |
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Scroll Only |
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- CologneChip GateMate FPGA, U1
- QSPI Flash, U5
- Power Switch, Q1
- DCDC, U7
- DCDC, U8
- Power Monitor, U9
- Oscillator, U10
- LEDs, D1-D2-D3
- B2B connector, JM2
- B2B connector, JM1
- Level shifter, U2
- Optional additional Flash, U4
- BUS-Transceiver, U6
- Oscillator, U3
Initial Delivery State
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Note |
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Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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anchor | Table_OV_IDS |
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title-alignment | center |
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title | Initial delivery state of programmable devices on the module |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Storage device name | Content | Notes |
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Quad SPI Flash | Blinky Demo Design | U5 |
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Signals, Interfaces and Pins
Connectors
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anchor | Table_SIP_C |
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title-alignment | center |
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title | Board Connectors |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Connector Type | Designator | Interface | IO CNT | Notes |
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Samtec 100 Pin B2B connectorB2B | JM1, Group 7 | SerDes | 8 |
| Samtec 100 Pin B2B connectorB2B | JM1, Group 1 | GPIO | 48 | Bank NB/EB/EA, powered by VCCIOA | Samtec 100 Pin B2B connectorB2B | JM1, Group 6 | GPIO | 6 | up to 3.3V due to level shifter, connected to Bank SB | Samtec 100 Pin B2B connectorB2B | JM1, Group 5 | GPIO | 6 | up to 1.8V, also connected to Bank SB | Samtec 100 Pin B2B connectorB2B | JM1 | configuration Signals | 3 | EN1, PGOOD , MODE | Samtec 100 Pin B2B connectorB2B | JM2, Group 4 | GPIO | 50 | Bank NA/WB/WC, powered by VCCIOD | Samtec 100 Pin B2B connectorB2B | JM2, Group 3 | GPIO | 18 | Bank SA, powered by VCCIOC | Samtec 100 Pin B2B connectorB2B | JM2 | JTAG | 4 | 0..3.3VIN | B2B | Samtec 100 Pin B2B connector | JM2 | MR | 1 | low active Reset | Samtec 100 Pin B2B connectorB2B | JM1 | CLK | DIFF CLK |
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Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delete the Test Point section. Example: Test Point | Signal | Notes1) |
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TP1 | PWR_PL_OK |
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1) Direction: - IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
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anchor | Table_SIP_TPs |
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title-alignment | center |
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title | Test Points Information |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Test Point | Signal | Side | Notes1) |
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TP1 | NA_6_N TP1 | top | FPGA IO | TP2 | NA_6_P | top | FPGA IO | TP3 | NB_B3 | top | FPGA IO | TP4 | NB_A3 | top | FPGA IO | TP5 | 1V | bottom | 1V power rail | TP6 | DONE | bottom | FPGA CFG_DONE pin | TP7 | PROG_B | bottom | FPGA RST_N pin | TP8 | GND | bottom |
| TP9 | GND | bottom |
| TP10 | 1V | top | 1V power rail | TP11 | 1.8V | top | OUT, 1.8V power rail | TP12 | VIN | top | VIN (3.3 - 5.0V) | TP13 | 3.3VIN | top |
| TP14 | 3.3V | top | OUT, 3.3V power rail | TP15 | VCCIOA | top | IN 1.1V ... 2.7V, powers IO Banks NB/EB/EA | TP16 | VCCIOC | top | IN 1.1V ... 2.7V, powers IO Bank SA | TP17 | VCCIOD | top | IN 1.1V ... 2.7V, powers IO Banks NA/WB/WC | TP18 | DONE | top | FPGA CFG_DONE pin | TP19 | PROG_B | top | FPGA RST_N pin | TP20 | GND | top |
| TP21 | GND | top |
| TP22 | FAILED_n | bottom | FPGA CFG_FAILED pin | TP23 | FAILED_n | top | FPGA CFG_FAILED pin |
1) Direction: - IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
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On-board Peripherals
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection Example: Chip/Interface | Designator | Connected To | Notes |
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ETH PHY | U10 | | Gigabit ETH PHY |
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anchor | Table_OBP |
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title-alignment | center |
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title | On board peripherals |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Chip/Interface | Designator | Connected To | Notes |
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QSPI Flash | U5 | FPGA Bank CFG WA | SPIx4 Interface for FPGA configuration | Oscillator | U3 | FPGA Bank SB, Pin IO_SB_A8 | 25 MHz | Oscillator | U10 | JM1, Pin 16 & 18 | differential 100 MHz Clock for Gigabit-Transceiver |
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Configuration and System Control Signals
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- Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
- In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)
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anchor | Table_OV_CNTRL |
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title-alignment | center |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Connector+Pin | Signal Name | Direction1) | Description |
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JM1.28 | EN1 | IN | activates DC-DCs | JM1.30 | PGOOD | OUT | Output from power monitor | JM1.32 | MODE | IN | configuration mode - 0 → JTAG or 1 → SPI active Mode | JM2.18 | MR | IN | low active Reset connected to the Power Monitor that triggers PROG_B (FPGA RST_N) | JM2.93 / JM2.95 / JM2.97 / JM2.99 | TMS / TDI / TDO / TCK | Signal-dependent | JTAG configuration and debugging interface. JTAG reference voltage: 3.3V |
1) Direction: - IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
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Power and Power-On Sequence
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Enter the default value for power supply and startup of the module here. - Order of power provided Voltages and Reset/Enable signals
Link to Schematics, for power images or more details |
Power Rails
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List of all power rails which are accessible by the customer - Main Power Rails and Variable Bank Power
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Scroll Title |
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anchor | Table_PWR_PR |
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title-alignment | center |
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title | Module power rails. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Rail Name/ Schematic Name | Connector + Pin | Direction1) | Notes |
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VIN | JM1.1 / JM1.3 / - 1,3,5; JM2 - 2,4,6,JM1.5 / JM2.2 /JM2.4 /JM2.6 / JM1.8 | IN | 3.3-5.0V, Micromodule Power | 3.3VIN | JM1 - .13 ,/JM1.15 | IN | Micromodule Power | VCCIOA | JM1 - .9 ,/ JM1.11 | IN |
| VCCIOC | JM2 - .5 | IN |
| VCCIOD | JM2 - .7 ,/JM2.9 | IN |
| 3.3V | JM2 - .10 ,12,/ JM2.12 / JM2.91 | OUT | Power for Carrier, powers on module the level shifter, LEDs and control Pins | 1.8V | JM1 - .39 | OUT | Power for Carrier, On module it powers on module the Flash, FPGA VDD and Banks SB,WA | 1V | -- | -- | Powers on module the FPGA core, PLLs and SerDes interface |
1) Direction: - IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
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Recommended Power up Sequencing
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List baseboard design hints for final baseboard development. |
According to CologneChip ds1001, there are no restrictions concerning order of voltage switch-on.
scroll-scroll-title |
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anchor | Table_BB_DH |
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title-alignment | center |
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title | Baseboard Design Hints |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes | 1
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0 | 3.3VIN | 3.3V(± 5 %)- | - | - | -Main power supply | | Configuration signal setup. | See Configuration and System Control Signals. | 1 | Main module power supply. 0.5 A minimum. Power consumption depends mainly on design and cooling solution. | 2 | VIN | 3.3 - 5.0V(± 5 %) | -- | Main power supply |
| 1 | EN1 | - | PU 1), 3.3VIN | power enable |
| 1 | PGOOD | - | PU 1), 3.3V | power good status. |
| 2 | 3.3VIN | 3.3V(± 5 %) | - | Main power supply | Main module power supply. 0.5 A minimum. Power consumption depends mainly on design and cooling solution. | 3 | VCCIOA, | 3 | VCCIOA, VCCIOC, VCCIOD | 1.1V - 2.7V | -- | Bank Voltages | 1.8V on TE0703 Carrier |
1) (on module) |
Board to Board Connectors
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- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 4 x 5 SoM LSHM B2B Connectors
Include Page |
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| 4 x 5 SoM LSHM B2B Connectors |
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| 4 x 5 SoM LSHM B2B Connectors |
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Include Page |
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| 4 x 5 SoM LSHM B2B Connectors |
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| 4 x 5 SoM LSHM B2B Connectors |
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Technical Specifications
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List of all power rails which are accessible by the customer - Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)
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Absolute Maximum Ratings *)
Scroll Title |
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anchor | Table_TS_AMR |
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title-alignment | center |
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title | Absolute maximum ratings |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Rail Name/ Schematic Name | Description | Min | Max | Unit |
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VIN | Micromodule Power | -0.3,135 | 6.5,25 | V | 3.3VIN | Micromodule Power | -0.3,1353,465 | 6.5 | V | VCCIOA | Bank NB/EB/EA voltage | 1.1 | 2.75 | V | VCCIOC | Bank SA voltage | 1.1 | 2.75 | V | VCCIOD | Bank NA/WB/WC voltage | 1.1 | 2.75 | V |
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*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
- Variants of modules are described here: Article Number Information
- Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
- Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
- Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
- The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.
Scroll Title |
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anchor | Table_TS_ROC |
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title-alignment | center |
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title | Recommended operating conditions. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Parameter | Min | Max | Units | Reference Document |
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VIN | 3,135 | 5,25 | V | See page 2 in schematic - Supported Voltage Ranges | 3.3VIN | 3,135 | 3,465 | V | " | VCCIOA | 1.1 | 2.75 | V | " | VCCIOC | 1.1 | 2.75 | V | " | VCCIOD | 1.1 | 2.75 | V | " |
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Physical Dimensions
PCB thickness: 1.4 mm.
All dimensions are shown in millimeters.
Scroll Title |
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anchor | Figure_TS_PD |
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title-alignment | center |
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title | Physical Dimension |
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draw.io Diagram |
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border | true |
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diagramName | TEG2000_phy_dim |
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simpleViewer | false |
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width | 600 |
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links | auto |
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tbstyle | top |
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lbox | true |
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diagramWidth | 1113 |
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revision | 2 |
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Scroll Only |
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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Currently Offered Variants
Scroll Title |
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anchor | Table_VCP_SO |
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title-alignment | center |
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title | Trenz Electronic Shop Overview |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Revision History
Hardware Revision History
Scroll Title |
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anchor | Figure_RV_HRN |
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title-alignment | center |
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title | Board hardware revision number. |
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Scroll Title |
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anchor |
title-alignment | center |
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title | Board hardware revision number. | simpleViewer | false |
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width | |
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links | auto |
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tbstyle | top |
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lbox | true |
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diagramWidth | 281 |
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revision | 1 |
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Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixedImage Added |
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Scroll Title |
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anchor | Table_RH_HRH |
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title-alignment | center |
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title | Hardware Revision History |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Revision | Changes | Documentation Link |
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- |
01 | | - | REV01 | First Production Release | REV01 | TEG2000-01
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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Scroll Title |
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anchor | Table_RH_DCH |
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title-alignment | center |
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title | Document change history. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Revision | Contributor | Description |
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Page info |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| Page info |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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showVersions | false |
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| Page info |
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infoType | Modified by |
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type | Flat |
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showVersions | false |
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| | -- | all | Page info |
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infoType | Modified users |
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type | Flat |
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showVersions | false |
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Disclaimer
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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