...
On-board I2C bus is accaessable with the following pins:
SDA | SCL | Notes |
---|---|---|
J1-144 | J1-142 | B2B |
J6-7 | J6-5 | In-Circuit Programming |
J21-10, J21-4 | J21-9, J21-3 | Pmod |
Table 8: I2C pins.
There are no I2C devices on the base board. Pullup resistors have to be provided by the module.
HTML |
---|
<!--
Components on the Module, like Flash, PLL, PHY...
--> |
...
--> |
The GPIOs of the 10 Pmods (J10 to J17, J20, J21) are connected with 100 Ohm differential routing to the B2B connector.J21 is a pure I2C compatible Pmod, without additional signals. The other 9 are GPIO Pmods where despite J20 all others can be used as dual Pmods. By default VCCIO_35 is connected with a 0 Ohm resistor to 3.3V. De-soldering this resistor and using pinheader J19 instead, the variable bank power VCCIO_35 for the Pmods J10, J11, J12, J13, J14, J16 can be selected.
J10 | J11 | J12 | J13 | J14 | J15 | J16 | J17 | J20 | J21 | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PIN | Signal | B2B | Signal | B2B | Signal | B2B | Signal | B2B | Signal | B2B | Signal | B2B | Signal | B2B | Signal | B2B | Signal | B2B | Signal | B2B |
1 | PA0_P | J1-56 | PB2_N | J1-70 | PC2_P | J1-57 | PD2_P | J1-77 | PE2_N | J1-90 | PG2_N | J1-110 | PF2_P | J1-97 | PH2_P | J1-115 | PI2_P | J1-133 | NC | - |
2 | PA0_N | J1-58 | PB2_P | J1-72 | PC2_N | J1-55 | PD2_N | J1-75 | PE2_P | J1-92 | PG2_P | J1-112 | PF2_N | J1-95 | PH2_N | J1-113 | PI2_N | J1-131 | NC | - |
3 | PA3_P | J1-46 | PB0_N | J1-76 | PC0_P | J1-51 | PD0_P | J1-71 | PE0_N | J1-96 | PG0_P | J1-114 | PF0_P | J1-91 | PH0_P | J1-111 | PI0_P | J1-129 | I2C_SCL | J1-142 |
4 | PA3_N | J1-48 | PB0_P | J1-78 | PC0_N | J1-49 | PD0_N | J1-69 | PE0_P | J1-98 | PG0_N | J1-116 | PF0_N | J1-89 | PH0_N | J1-109 | PI0_N | J1-127 | I2C_SDA | J1-144 |
5 | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - |
6 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | 3.3V | J1-74, J1- 43 | VCCIO_35 | J1-54 | 3.3V | J1-74, J1- 43 | 3.3V | J1-74, J1- 43 | 3.3V | J1-74, J1- 43 |
7 | PA1_N | J1-62 | PB3_P | J1-68 | PC3_N | J1-59 | PD3_N | J1-79 | PE3_P | J1-88 | PG3_P | J1-108 | PF3_N | J1-99 | PH3_N | J1-117 | PI3_N | J1-135 | NC | - |
8 | PA1_P | J1-60 | PB3_N | J1-66 | PC3_P | J1-61 | PD3_P | J1-81 | PE3_N | J1-86 | PG3_N | J1-106 | PF3_P | J1-101 | PH3_P | J1-119 | PI3_P | J1-137 | NC | - |
9 | PA2_N | J1-52 | PB1_P | J1-82 | PC1_N | J1-45 | PD1_N | J1-65 | PE1_P | J1-102 | PG1_N | J1-120 | PF1_N | J1-85 | PH1_N | J1-105 | PI1_N | J1-123 | I2C_SCL | J1-142 |
10 | PA2_P | J1-50 | PB1_N | J1-80 | PC1_P | J1-47 | PD1_P | J1-67 | PE1_N | J1-100 | PG1_P | J1-121 | PF1_P | J1-87 | PH1_P | J1-107 | PI1_P | J1-125 | I2C_SDA | J1-144 |
11 | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - |
12 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | 3.3V | J1-74, J1- 43 | VCCIO_35 | J1-54 | 3.3V | J1-74, J1- 43 | 3.3V | J1-74, J1- 43 | 3.3V | J1-74, J1- 43 |
Table 9: Pmod connections.
The TEB0724 carrier board has on-board microUSB 2.0 (J4) high-speed to UART/FIFO IC FT2232H (U1) from FTDI. Channel A can be used as JTAG Interface (MPSSE) to program on module JTAG devices. Channel B can be used as UART Interface routed to via a level shifter to the 1.8V section of the B2B connector, usually connected to the PS of the SoM. There is also a 256-byte serial EEPROM connected to the FT2232H chip pre-programmed with license code to support Xilinx programming tools.
Warning |
---|
Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content. |
The CAN bus is routed to screw terminal J2.
PIN | Signal | B2B |
---|---|---|
J2-1 | CAN0_N | J1-1 |
J2-2 | GND | |
J2-3 | CAN0_P | J1-3 |
Table 9: CAN bus connection.
Proper termination of the can bus can be set via jumpers on J22 according to the device position on the bus. Jumpers on J22-1 to J22-3 and J22-2 to J22-4 connect proper split termination resistors to the CAN bus.
The module has the following reference clock signals provided by on-board oscillators:
...
For voltage selection VCCIO_35 of Bank 35 other than 3.3V the header J19 can optionaly assembled. Therefore 0 Ohm resistor R45 has to be removed!
PIN | Signal | B2B |
---|---|---|
J19-1 | VLDO1 | J1-83 |
J19-2 | GND | |
J19-3 | VCCIO_35 | J1-54 |
J19-4 | VLDO2 | J1-94 |
J19-5 | VLDO34 | J1-53 |
J19-6 | GND |
Table 13: Optional Pin Header J19.
...
PL Button and LED IOs are additionally routed to optionally assembled pin header J8.
PIN | Signal | B2B |
---|---|---|
J8-1 | 3.3V | J1-43, J1-74 |
J8-2 | GND | |
J8-3 | S4 | J1-126 |
J8-4 | S2 | J1-124 |
J8-5 | ULED5 | J1-130 |
J8-6 | ULED6 | J1-128 |
J8-7 | ULED3 | J1-134 |
J8-8 | ULED4 | J1-132 |
J8-9 | ULED1 | J1-138 |
J8-10 | ULED2 | J1-136 |
Table 14: Optional Pin Header J8.
...
Optional pin header J7 gives access to otherwise not used PS MIO IOs at a 3.3V bank.
PIN | Signal | B2B |
---|---|---|
J7-1 | 3.3V | 43, 74 |
J7-2 | GND | |
J7-3 | GND | |
J7-4 | MIO8 | J1-14 |
J7-5 | MIO10 | J1-31 |
J7-6 | MIO11 | J1-33 |
J7-7 | MIO12 | J1-35 |
J7-8 | MIO13 | J1-37 |
J7-9 | MIO14 | J1-39 |
J7-10 | MIO15 | J1-41 |
Table 15: Optional Pin Header J7.
...
Optional pin header J9 gives access to otherwise not used PS MIO IOs at a 1.8V bank.
PIN | Signal | B2B |
---|---|---|
J9-1 | 1.8V | J1-63 |
J9-2 | GND | |
J9-3 | GND | |
J9-4 | MIO_46 | J1-32 |
J9-5 | MIO_50 | J1-40 |
J9-6 | MIO_PB | J1-42 |
Table 16: Optional Pin Header J9.
...