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The GPIOs of the 10 Pmods (J10 to J17, J20, J21) are connected with 100 Ohm differential routing to the B2B connector. J21 is a pure I2C compatible Pmod, without additional signals. The other 9 are GPIO Pmods where despite J20 all others can be used as dual Pmods. By default VCCIO_35 is NOT connected with a 0 Ohm resistor to 3.3V. De-soldering this resistor and using not fitted . Via pin header J19 instead, the variable bank power VCCIO_35 for the Pmods J10, J11, J12, J13, J14, J16 can be selected. Respect power regulator limits!
| J10 | J11 | J12 | J13 | J14 | J15 | J16 | J17 | J20 | J21 | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PIN | Signal | B2B | Signal | B2B | Signal | B2B | Signal | B2B | Signal | B2B | Signal | B2B | Signal | B2B | Signal | B2B | Signal | B2B | Signal | B2B |
| 1 | PA0_P | J1-56 | PB2_N | J1-70 | PC2_P | J1-57 | PD2_P | J1-77 | PE2_N | J1-90 | PG2_N | J1-110 | PF2_P | J1-97 | PH2_P | J1-115 | PI2_P | J1-133 | NC | - |
| 2 | PA0_N | J1-58 | PB2_P | J1-72 | PC2_N | J1-55 | PD2_N | J1-75 | PE2_P | J1-92 | PG2_P | J1-112 | PF2_N | J1-95 | PH2_N | J1-113 | PI2_N | J1-131 | NC | - |
| 3 | PA3_P | J1-46 | PB0_N | J1-76 | PC0_P | J1-51 | PD0_P | J1-71 | PE0_N | J1-96 | PG0_P | J1-114 | PF0_P | J1-91 | PH0_P | J1-111 | PI0_P | J1-129 | I2C_SCL | J1-142 |
| 4 | PA3_N | J1-48 | PB0_P | J1-78 | PC0_N | J1-49 | PD0_N | J1-69 | PE0_P | J1-98 | PG0_N | J1-116 | PF0_N | J1-89 | PH0_N | J1-109 | PI0_N | J1-127 | I2C_SDA | J1-144 |
| 5 | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - |
| 6 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | 3.3V | J1-74, J1- 43 | VCCIO_35 | J1-54 | 3.3V | J1-74, J1- 43 | 3.3V | J1-74, J1- 43 | 3.3V | J1-74, J1- 43 |
| 7 | PA1_N | J1-62 | PB3_P | J1-68 | PC3_N | J1-59 | PD3_N | J1-79 | PE3_P | J1-88 | PG3_P | J1-108 | PF3_N | J1-99 | PH3_N | J1-117 | PI3_N | J1-135 | NC | - |
| 8 | PA1_P | J1-60 | PB3_N | J1-66 | PC3_P | J1-61 | PD3_P | J1-81 | PE3_N | J1-86 | PG3_N | J1-106 | PF3_P | J1-101 | PH3_P | J1-119 | PI3_P | J1-137 | NC | - |
| 9 | PA2_N | J1-52 | PB1_P | J1-82 | PC1_N | J1-45 | PD1_N | J1-65 | PE1_P | J1-102 | PG1_N | J1-120 | PF1_N | J1-85 | PH1_N | J1-105 | PI1_N | J1-123 | I2C_SCL | J1-142 |
| 10 | PA2_P | J1-50 | PB1_N | J1-80 | PC1_P | J1-47 | PD1_P | J1-67 | PE1_N | J1-100 | PG1_P | J1-121 | PF1_P | J1-87 | PH1_P | J1-107 | PI1_P | J1-125 | I2C_SDA | J1-144 |
| 11 | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - |
| 12 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | 3.3V | J1-74, J1- 43 | VCCIO_35 | J1-54 | 3.3V | J1-74, J1- 43 | 3.3V | J1-74, J1- 43 | 3.3V | J1-74, J1- 43 |
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For voltage selection VCCIO_35 (SoM TE0724, Bank 35) other than 3.3V the header J19 can optionaly assembled. Therefore 0 Ohm resistor R45 has to be removed!can be selected by adding a jumper on J19.
| PIN | Signal | B2B |
|---|---|---|
| J19-1 | VLDO1 | J1-83 |
| J19-2 | GND | |
| J19-3 | VCCIO_35 | J1-54 |
| J19-4 | VLDO2 | J1-94 |
J19-5 | VLDO34 | J1-53 |
| J19-6 | GND |
Table 15: Optional Pin Header J19.
| Warning |
|---|
Respect VLDO limitations! |
Optional fitted headers J7, J8 and J9 are to provide full access to the Pins at the B2B connector, especially for testing and extension purposes. Description follows below.
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User should also check related module documentation and Xilinx data sheet, respectively.
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The power-on sequence is solely controlled by the attached module. Optional sequenzing signals for integration of additional hardware are PWR_GPIO2 and PWR_GPIO4. If the attached module uses the adjustable bank power VCCIO_35, this has to be powered up after the modules SOCs powerrails are up and before any other signal is applied to the bank IOs. The 1.8V and 3.3V power rails are used for the SD Card level shifter U13. The datasheet states to first power up 1.8V and then 3.3V, this has to be taken into account when reconfiguring the power circuit of the attached SoM.
Power-Off is in reverse order. VCCIO_35 has to be disabled before the SoCs core voltages are turned off.
Power Rails
Power Rail Name | B2B J1 Pins | Direction on B2B | Notes |
|---|---|---|---|
| VIN | 154, 156, 158, 160 | Output | External main supply voltage. |
| 3.3V | 43, 74 | Input | |
1.8V | 63 | Input | |
| VCCIO_35 | 54 | Output | |
VLDO1 | 83 | Input | |
| VLDO2 | 94 | Input | Used to enable UART level shifter. Therefore fix at 1.8V. |
| VLDO34 | 53 | Input | |
VBAT | 152 | Input/Output | Reserved for PMIC backup battery and charger. |
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Date | Revision | Contributors | Description | ||||||||||||||||||||||||||
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| v.25 | Martin Rohrmüller |
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| v.24 | Martin Rohrmüller |
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v.23 | John Hartfiel |
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2018-07-10 | v.19 |
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