Page History
...
The voltages 'LP_DCDC' and 'LP_0V85' are monitored by a the voltage monitor circuit U41, which generates the POR_B reset signal at Power-On. A manual reset is also possible by driving the MR-pin (J2-83) to GND. Leave this pin unconnected or connect to VDD (LP_DCDC) when unused.
...
Overview
Content Tools