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Overview

The Trenz Electronic TE0808 is an industrial grade SoM integrating an AMD Zynq UltraScale+ MPSoC, DDR4 SDRAM with 64-Bit width data bus connection, SPI Boot Flash memory for configuration and operation, MGT Transceivers and powerful DCDC power converters for most on-board voltages. A large number of configurable IOs is provided via rugged high-speed stacking connections in a compact 5.2 cm x 7.6 cm form factor.

Refer to https://trenz.org/te0808-info for the current online version of this manual and other available documentation.

Key Features

  • SoC
    • AMD Zynq UltraScale+ MPSoC (XC) 1) 2) 3) : ZU6 / ZU9 / ZU15
    • Engine 1):                      CG / EG
    • Speed-grade 1):            -1 / -2
    • Temperature Range 1): E / I
    • Package:                       FFVC900
  • RAM/Storage
    • 4x DDR4 SDRAM 4 GByte (4x 512 M x 16 bit) 1) 4)
    • 2x QSPI Flash 64 MByte (with XiP support) 1)
    • Serial EEPROM 2 Kbit with unique EUI-48 ™ / MAC address
  • On Board
    • Trusted Platform Module 2.0 device
    • Programmable Clock Generator
    • Clocks for SoC PS, Programmable Clock Generator and MGT Transceiver
    • 1x LED status red
  • Interface
    • Trenz 5.2 x 7.6 SoM 4x B2B Connector (Samtec ST5) socket:
      • MIO:     65x SE
      • IO HP: 156x SE / 72x DIFF
      • IO HD:   48x SE / 24x DIFF
      • MGT:     16x GTH and 4x CLK (SoC PL)
                       4x GTR and 2x CLK (SoC PS)
  • Power
    • Single Rail 3.3 V power supply 5)
    • Voltage Monitoring and Watchdog
  • Dimension
    • 52 mm x 76 mm
  • Notes

1) Available as assembly variant or upon request.
2) Check whether the power supply is powerful enough for your FPGA design.
3) Without PCIe Core on PL, see AMD Product Selection Guide (XMP104)
4) Up to 8 GByte are possible with a maximum bandwidth of 2400 Mbit/s.
5) Dependent on the assembly option, a higher input voltage may be possible

Block Diagram

 


TE0808 block diagram

Main Components

 

TE0808 main components
  1. SoC, U1
  2. DDR4, U2, U3, U9, U12
  3. Quad SPI Flash, U7, U17
  4. B2B connectors - Samtec ST5, J1, J2, J3, J4
  5. EEPROM, U4
  6. Clock Generator, U5
  7. Oscillator, U25, U32
  8. Crystal, Y1
  9. LED - Status DONE, D1

Initial Delivery State

Storage device

Designator

Content

Notes

Programmable Clock GeneratorU5Not programmed


QSPI Flash

U7 / U17

Not programmed


EEPROMU4MAC is burned-in by the manufacturer.


Initial delivery state of programmable devices

Signals, Interfaces and Pins

Connectors

Connector Type

Designator

Interface

IO count

Notes

B2B

J1

IO HP

52x SE / 24x DIFF

Bank 66

B2B

J1

MGT

12x GTH (RX/TX)


B2B

J3

IO MIO

13x SE

Bank 500

B2B

J3

IO MIO

26x SE

Bank 501

B2B

J3

IO MIO

26x SE

Bank 502

B2B

J3

IO HD

48x SE / 24x DIFF

Bank 47

B2B

J3

IO HD

48x SE / 24x DIFF

Bank 48

B2B

J3

MGT CLK

3x DIFF


B2B

J3

IO CLK in

1x DIFF


B2B

J2

MGT CLK

3x DIFF


B2B

J2

MGT

4x GTH (RX/TX)

Bank 128

B2B

J2

MGT

4x GTR (RX/TX)

Bank 505

B2B

J2

IO CLK out

3x DIFF


B2B

J2

IO CLK in

1x DIFF


B2B

J4

IO HP

52x SE / 24x DIFF

Bank 64

B2B

J4

IO HP

52x SE / 24x DIFF

Bank 65

Board connectors

Test Points

Test

point

REV06

REV05

signal

REV04

signal

REV03

signal

REV02

signal


Notes

Top

Bottom

signal

TP1


x

PLL_SCL


TP2


x

PLL_SDA


TP3


x

LP_DCDC


TP4


x

DCDCIN


TP5


x

GND


TP6


x

TCK


TP7


x

PL_DCIN


TP8


x

GND


TP9


x

GT_DCDC


TP10


x

GND


TP11


x

TDI


TP12


x

TDO


TP13


x

TMS


TP14


x

PS_1V8


TP15


x

U33.2 / U1A.V16

Not used

GND


TP16


x

FP_0V85

Not used


TP17


x

DDR_2V5

Not used


TP18


x

DDR_PLL

Not used


TP19


x

PL_VCCINT

Not used


TP20


x

AUX_R

Not used


TP21


x

AVTT_R

Not used


TP22


x

AUX_L

Not used


TP23


x

DDR4-TEN

Not used


TP24


x

AVCC_R

Not used


TP25

x


PL_VCCINT

Not used


TP26


x

AVTT_L

Not used


TP27

-

-

Not used


TP28


x

AVCC_L

Not used


TP29

-

-

Not used


TP30


x

PS_PLL

Not used


TP31


x

PS_AVTT

Not used


TP32


x

LP_0V85

Not used


TP33


x

PS_AUX

Not used


TP34


x

PS_AVCC

Not used


TP35

-

-

Not used


TP36


x

POR_B

Not used


TP37

x


PL_VCCINT

Not used


TP38

x


PL_DCIN

Not used


TP39

x


PL_1V8

Not used


TP40

x


DCDCIN

Not used


TP41

x


DCDC_2V0

Not used


TP42

x


FP_0V85

Not used


TP43

x


PS_GT_1V0

Not used


TP44

x


GT_DCDC

Not used


TP45

x


DDR_2V5

Not used


TP46

x


DDR_1V2

Not used


TP47

x


VTT

Not used


TP48


x

VTT

Not used


TP49

x


VREFA

Not used


TP50


x

VREFA

Not used


TP51

x


SI_PLL_1V8

Not used


TP52

x


PL_GT_1V35

Not used


TP53

x


PL_GT_1V05

Not used


TP54

x


PL_GT2_1V35

Not used


TP55

x


PL_GT2_1V05

Not used


TP56

x


AVTT_R

Not used


TP57

x


AVCC_R

Not used


TP58

x


AVTT_L

Not used


TP59

x


AVCC_L

Not used


TP60

x


AUX_R

Not used


TP61

x


AUX_L

Not used


TP62

x


PS_1V8

Not used


TP63

x


LP_0V85

Not used


TP64

x


PS_AVTT

Not used


TP65

x


PS_AUX

Not used


TP66

x


PS_AVCC

Not used


TP67

x


U47.7

Not used


Test points information

On-board Peripherals

Chip/Interface

Designator

Connected to

Notes

SoC

U1

  • DDR4 SDRAM U2, U3, U9, U12
  • QSPI flash U7, U17
  • I2C
  • Oscillator U32
  • Programmable Clock Generator U5
  • B2B J1, J2, J3, J4


DDR4 SDRAM

U2 / U3 / U9 / U12

  • SoC U1


SPI Flash

U7 / U17

  • SoC U1


EEPROM with MAC

U4

  • I2C


Trusted Platform Module 2.0

U47

  • I2C
  • B2B J3


Programmable Clock Generator

U5

  • SoC U1
  • Oscillator quartz Y1
  • Oscillator U25
  • I2C
  • B2B J2, J3


Oscillator

U32

  • SoC U1

33⅓ MHz

Oscillator

U25

  • Programmable clock generator U5

25 MHz

Oscillator quartz

Y1

  • Programmable clock generator U5

25 MHz

On-board peripherals

Configuration and System Control Signals

Control signals represent hardware defined logic states, for final state consider firmware and reference designs.

Control Signals and Buses

Signal Name

Connector.Pin

Direction1)Description
JM2.77EN_PLL_PWRINEnable PLL power supply.
JM2.79EN_GT_LINEnable left GTH transceiver power-up.
JM2.80PG_PLL_1V8OUTSI_PLL_1V8 power rail powered-up.
JM2.81PLL_FINCINPLL Frequency incrementation.
JM2.82PG_PSGTOUTGTR transceivers powered-up.
JM2.83MRINManual reset.
JM2.84EN_PSGTINEnable GTR transceiver power-up.
JM2.85PLL_LOLnOUTLoss of lock status.
JM2.86ERR_STATUSOUTPS error status 2).
JM2.87PLL_SEL1INPLL clock selection.
JM2.88ERR_OUTOUTPS error indication 2).
JM2.89PLL_RSTINPLL reset.
JM2.90PLL_SCLINI2C clock. Pulled up to PS_1V8.
JM2.91PG_GT_ROUTRight GTH Transceivers powered-up.
JM2.92PLL_SDAIN/OUTI2C data. Pulled up to PS_1V8.
JM2.93PLL_SEL0INPLL clock selection.
JM2.94PLL_FDECINPLL Frequency decrementation.
JM2.95EN_GT_RINEnable right GTH transceiver power-up.
JM2.96SRST_BINSystem reset 2). Pulled-up to PS_1V8.
JM2.97PG_GT_LOUTLeft GTH Transceivers powered-up.
JM2.98INIT_BIN/OUTInitialisation completion indicator after POR 2). Pulled-up to PS_1V8.
JM2.100PROG_BIN/OUTPower-on reset 2). Pulled-up to PS_1V8.
JM2.101EN_PLINEnable programmable logic power-up.
JM2.102EN_FPDINEnable full-power domain power-up.
JM2.103 / JM2.105 / JM2.107 / JM2.109MODE3..0INBoot mode selection 2):
  • JTAG
  • QUAD SPI (32 Bit)
  • SD1 (2.0)
  • e.MMC (1.8 V)
  • SD1 LS (3.0)

Supported Modes depends also on used Carrier.

JM2.104PG_PLOUTProgrammable logic powered-up. Pulled-up to PL_DCIN.
JM2.106LP_GOODOUTLow-power domain powered-up. Pulled up to LP_DCDC.
JM2.108EN_LPDINEnable low-power domain power-up.
JM2.110PG_FPDOUTFull-power domain powered-up. Pulled-up to DCDCIN.
JM2.112EN_DDRINEnable DDR power-up.
JM2.114PG_DDROUTDDR power supply powered-up. Pulled-up to DCDCIN.
JM2.116DONEOUTPS done signal 2). Pulled-up to PS_1V8.
JM2.119 / JM2.121DX_P / DX_N-SoC temperature sensing diode pins 2).
JM2.120 / JM2.122 /
JM2.124 / JM2.126
TCK / TDI / TDO / TMSSignal-dependent

JTAG configuration and debugging interface.

JTAG reference voltage: PS_1V8

JM2.125PSBATTINPS RTC Battery supply voltage 2) 3).
JM2.127PUDC_BINConfiguration pull-ups setting 2). Pulled-up to PL_1V8.
JTAG ( TCK / TDI / TDO / TMS )JM2.120 / JM2.122 / JM2.124 / JM2.126Signal dependent
MODE3 / MODE2 / MODE1 / MODE0JM2.103 / JM2.105 / JM2.107 / JM2.109IN
I2C ( PLL_SCL / PLL_SDA)JM2.90 / JM2.92Signal dependentI2C net with Programmable Clock Generator, EEPROM and TPM 2.0 module.

1) Direction:

    • IN: Input from the point of view of this board.

    • OUT: Output from the point of view of this board.

    • INOUT: Bidirectional signal.
    • Signal dependent: A Signal can have different functions and directions as part of a Bus.

2) See UG1085 for additional information.

3) See Recommended Operating Conditions.

Control signals and buses

Power and Power-On Sequence

Power Rails

Power Rail Name/ Schematic NameConnector.PinDirection1)Notes
DCDCINJM2.153 / JM2.154 / JM2.155 / JM2.156 / JM2.157 / JM2.158 / JM2.159 / JM2.160INMain  SoM supply
PL_DCINJM1.151 / JM1.153 / JM1.155 / JM1.157 / JM1.159INProgrammable logic supply
LP_DCDCJM2.138 / JM2.140 / JM2.142 / JM2.144INLow power SoC supply
GT_DCDCJM3.157 / JM3.158 / JM3.159 / JM3.160INMGT transceiver supply
PLL_3V3JM3.152INprogrammable clock generator supply
PS_BATTJM2.125INBackup voltage supply
VCCO_47JM3.43 / JM3.44INIO Supply
VCCO_48JM3.15 / JM3.16INIO Supply
VCCO_64JM4.58 / JM4.106INIO Supply
VREF_64JM4.88INIO reference voltage
VCCO_65JM4.69 / JM4.105INIO Supply
VREF_65JM4.15INIO reference voltage
VCCO_66JM1.90 / JM1.120INIO Supply
VREF_66JM1.108INIO reference voltage
DDR_1V2JM2.135OUTExternal IO supply
SI_PLL_1V8JM3.151OUTExternal IO supply

PL_1V8

JM1.91 / JM1.121OUTExternal IO supply
PS_1V8JM2.99 / JM3.147 / JM3.148OUTExternal IO supply

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.
Power rails

Recommended Power up Sequencing

The power up sequencing highly depends on the use case. In general, it should be possible to enable/disable the processing system (PS) / programmable logic (PL) independently. Furthermore, within the processing logic it should be possible to enable/disable only low-power domain and/or low-power and full-power domain. Additionally, usage of GTR for PS side and GTH for PL side should be possible. GTH transceivers on left and right side are usable independently. Because of this flexibility the needed parts of the following table needs to be selected individually. For detailed information take a look into schematics. Attention: PL usage is not completely independent of PS side. For PL usage it is necessary to enable PS low-power domain.

SequenceNet nameRecommended Voltage RangePull-up/downDescriptionNotes
0---Configuration signal setup.See Control Signals and Buses.
1 1)PSBATT1.2 V ... 1.5 V-Battery connection.Battery Power Domain usage. When not used, tie to GND.
2Processing System (PS):

Procedure for PS starting.
2.1Low-power domain:Bring-up for low-power domain PS.
2.1.1LP_DCDC3.3 V (± 5 %) 2)-Low-power domain power supply.Main module power supply for low-power domain. 5.5 A recommended. Power consumption depends mainly on design and cooling solution.
2.1.2EN_LPD--Low-power domain power enable.
2.1.3LP_GOOD-PU 3), LP_DCDCLow-power domain power good status.Module power-on sequencing for low-power domain finished.
2.2Full-power domain:Bring-up for full-power domain PS.Full-power PS domain needs powered low-power PS domain.
2.2.1DCDCIN3.3 V (± 5 %) 2)
Full-power domain and GTR transceiver power supply.Main module power supply for full-power domain. 7 A recommended. Power consumption depends mainly on design and cooling solution.
2.2.2EN_FPDDCDCIN-Full-power domain power enable.
2.2.3PG_FPD-PU 3), DCDCINFull-power domain power good status.Module power-on sequencing for full-power domain finished.
2.2.4EN_DDRDCDCIN-DDR memory power enable.
2.2.5PG_DDR-PU 3), DCDCINDDR memory power good status.Module power-on sequencing for DDR memory finished.

2.3

GTR TransceiverProcedure for GTR transceiver starting.PS transceiver usage needs powered PS (low- and full-power domain).
2.3.1EN_PSGTDCDCIN-GTR transceiver power enable.
2.3.2PG_PSGT--GTR transceiver power good status.Module power-on sequencing for GTR transceiver finished.
2Programmable Logic (PL)Procedure for PL starting.PL usage needs powered PS low-power domain.
2.1PL_DCIN3.3 V (± 5 %) 2)-Programmable logic power supply.Main module power supply for programmable logic. 12 A recommended. Power consumption depends mainly on design and cooling solution.
2.2EN_PL-PU 3), PL_DCINProgrammable logic power enable.
2.3PG_PL-PU 3), PL_DCINProgrammable logic power good status.Module power-on sequencing for programmable logic finished. Periphery and variable bank voltages can be enabled on carrier.
2.4VCCO_47 / VCCO_48 / VCCO_64 / VCCO_65 / VCCO_66 4)-Module bank voltages.Enable bank voltages after PG_PL deassertion.
3GTH / GTY TransceiverProcedure for GTH / GTY transceiver starting.PL transceiver usage needs powered PL and low-power PS domain.
3.1GT_DCDC3.3 V (± 5 %) 2)-GTH transceiver power supply.Main module power supply for GTH transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution.
3.21)EN_PLL_PWR--PLL power enable.
3.21)PG_PLL_1V8--PLL power good status.
3.21)PLL_3V33.3 V (± 5 %)
PLL power supply
3.3EN_GT_L / EN_GT_RGT_DCDC-GTH / GTY left / right transceiver power enable.Transceivers on left / right side can be used independently.
3.4PG_GT_L / PG_GT_R--GTH / GTY transceiver power good status.
4MR

Manual ResetLow active release after all needed power domains are enabled. 

1) Optional
2) Dependent on the assembly option a higher input voltage may be possible.
3) On module
4) See DS925 for additional information.

Baseboard Design Hints

Board to Board Connectors

5.2 x 7.6 cm UltraSoM+ modules use four Samtec Razor Beam LP Terminal Strip (ST5) on the bottom side.
  • 4x REF-192552-02 (160-pins)
    • ST5 Mates with SS5

5.2 x 7.6 cm UltraSoM+ carrier use four Samtec Razor Beam LP Socket Strip (SS5) on the top side.

  • 4x REF192552-01 (160-pins)
    • SS5 Mates with ST5
Features
  • Board-to-Board Connector 160-pins, 80 contacts per row
  • Ultrafine .0197" (0.50 mm) pitch
  • Narrow body design saves space on board
  • Lead style -03.5
  • Samtec 28+ Gbps Solution
  • Mates with: ST5
  • Insulator Material: Liquid Crystal Polymer, schwarz
  • Operating Temperature Range: -55°C bis +125°C
  • Lead-Free Solderable: Yes
  • RoHS Konform: Yes


Connector Stacking height

When using the standard type on baseboard and module, the mating height is 5 mm.

Other mating heights are possible by using connectors with a different height:

Order numberREF numberSamtec NumberTypeContribution to stacking heightComment
27219REF192552-01SS5-80-3.50-L-D-K-TRBaseboard connector3.5mm

Standard connector used on carrier

27018REF-189545-02 SS5-80-3.00-L-D-K-TRBaseboard connector3 mm 

Assembly option on request

27220REF-192552-02 ST5-80-1.50-L-D-P-TRModule connector1.5 mm

Standard connector used on modules

27017REF-189545-01 ST5-80-1.00-L-D-P-TRModule connector1 mm

Assembly option on request

Connectors.


The module can be manufactured using other connectors upon request.

Current Rating

Current rating of Samtec Razor Beam LP Terminal/Socket Strip ST5/SS5 B2B connectors is 1.5 A per pin (1 pin powered per row).

Connector Speed Ratings

The connector speed rating depends on the stacking height:

Stacking height

Speed rating

4 mm, Single-Ended13GHz/26Gbps
4 mm, Differential13.5GHz/27Gbps
5 mm, Single-Ended13.5GHz/27Gbps
5 mm, Differential20GHz/40 Gbps
Speed rating.

The SS5/ST5 series board-to-board spacing is currently available in 4mm (0.157"), 4.5mm (0.177") and 5mm (0.197") stack heights.

The data in the reports is applicable only to the 4mm and 5mm board-to-board mated connector stack height.

Manufacturer Documentation

  File Modified
PDF File hsc-report-sma_st5-ss5-04mm_web.pdf May 30, 2017 by Susanne Kunath
PDF File hsc-report-sma_st5-ss5-05mm_web.pdf May 30, 2017 by Susanne Kunath
PDF File REF-192552-01.pdf Nov 13, 2017 by John Hartfiel
PDF File REF-192552-02.pdf Nov 13, 2017 by John Hartfiel
PDF File ss5.pdf Nov 13, 2017 by John Hartfiel
PDF File ss5-st5.pdf Nov 13, 2017 by John Hartfiel
PDF File ss5-xx-x.xx-x-d-k-tr-mkt.pdf Nov 13, 2017 by John Hartfiel
PDF File st5.pdf Nov 13, 2017 by John Hartfiel
PDF File st5-xx-x.xx-x-d-p-tr-mkt.pdf Nov 13, 2017 by John Hartfiel


Technical Specifications

Absolute Maximum Ratings *)

Power Rail Name/ Schematic NameDescriptionMinMaxUnit
DCDCINMicromodule Power-0.3006.0V
PL_DCINMicromodule Power-0.300

3.6

V
LP_DCDCMicromodule Power-0.3004.0V
GT_DCDCMicromodule Power-0.3006.0V
PLL_3V3PLL power supply-0.5003.8V
PS_BATTRTC / BBRAM-0.5002.000V
VCCO_47HD IO Bank power supply-0.5003.400V
VCCO_48HD IO Bank power supply-0.5003.400V
VCCO_64HP IO Bank power supply-0.5002.000V

VCCO_65

HP IO Bank power supply-0.5002.000V
VCCO_66HP IO Bank power supply-0.5002.000V
VREF_64Bank input reference voltage-0.5002.000V
VREF_65Bank input reference voltage-0.5002.000V
VREF_66Bank input reference voltage-0.5002.000V
Absolute maximum ratings

*) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Condition". Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

Temperature range

Trenz Electronic classifies modules into temperature range categories by subsumption of its component data (PCB, ICs, connectors, passive components). The temperature ranges are values for ambient air temperature and do not reflect the junction temperature of individual components.

The categories are:

  • Modules with commercial (C) temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 70 °C.
  • Modules with extended (E) temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 85 °C.
  • Modules with industrial (I) temperature grade are equipped with components that cover at least the ambient temperature range of -40 °C to 85 °C.

These categories do not take into account the entire custom system consisting of:

  • Customer SoC design. The allowed main SoC temperature range is specified from the vendor by junction temperature using corresponding classes (C, E, I). See vendor documentation.
  • Cooling solution, active and or passive cooling.
  • Climate or environmental conditions besides ambient temperature range.
  • Module orientation, neighbouring assemblies, neither other heat sources nor the SoC as heat source to other components.

Classification of the module can be looked up here: Article Number Information i.e.: TExxxx-xx-xx'I'xx, the 'I' indicates that all components are at least in Industrial temperature class.

The temperature of individual components should not exceed the specified range due to self-heating or heating by adjacent components. The actual operating temperature range will depend on the customer design, usage, environment and cooling solution. Consult Cooling Solutions for more information.

Voltage rails

The following table aims to be generic for all variants. The voltage ranges are consistent across assembly variants, but exceptions are possible (custom request).

ParameterMinMaxUnitsReference Document
DCDCIN 1)3.15.5VSee SoM data-sheet.
PL_DCIN 1)2.55.5VSee SoM data-sheet.
LP_DCDC 1)3.13.6VSee SoM data-sheet.
GT_DCDC 1)3.15.5VSee SoM data-sheet.
PLL_3V33.143.46VSee SoM data-sheet.
PS_BATT1.201.50VSee SoM data-sheet.
VCCO_471.143.40VSee SoM data-sheet.
VCCO_481.143.40VSee SoM data-sheet.
VCCO_640.951.90VSee SoM data-sheet.

VCCO_65

0.951.90VSee SoM data-sheet.
VCCO_660.951.90VSee SoM data-sheet.
VREF_640.61.2VSee SoM data-sheet.
VREF_650.61.2VSee SoM data-sheet.
VREF_660.61.2VSee SoM data-sheet.
Recommended operating conditions

Physical Dimensions

  • Module size: 52.0 mm × 76.0 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 5 mm.

  • PCB thickness: 1.752 mm ±10 %.

 

Physical dimension

Currently Offered Variants 

Trenz shop TE0808 overview page*
English pageGerman page

*)  Module article name encoding table: Zynq Ultrascale+ based modules (MPSoC, RFSoC)

Trenz Electronic shop overview

Revision History

Hardware Revision History

The hardware revision number can be found on the PCB board together with the module's model number, separated by a dash.

 

Board hardware revision number


DateRevisionChangesDocumentation Link
2026-0306
  1. R103, R104 added (strap option POR_OVERRIDE).
  2. All TEN pins connected together. R105 and TP23 added.
  3. Net name REF_1V25 added (U33 pin 2).
  4. C195-C201 added according to AMD DDR routing recommendations.
  5. All capacitors X5R changed to X6S with the same size and voltage rating but with better temperature grade.
  6. TP25, TP37-TP66 added.
  7. Trace lengths changed.
  8. R109 - R112 added according to AMD recommendations.
  9. Legal Notices page, System overview, Power diagram added.
  10. Diode AND gate D2 BAT54AWT1G changed to AND gate SN74LV1T08DCKR for isolating different power domains from each other.
  11. U39, U40, U42, U43, U44 NC7S08P5X changed to SN74LV1T08DCKR, C112 16V 0402 to 10V 0201, R13 , R48 2k to 2k2, L6 , L8 MPZ1608S221A to MPZ0603S121HT000 for BOM optimisation.
  12. Diode D3 added according to U41 data sheet recommendation.
  13. R72, R73, R75, R77-R79, R88, R89, R93, R94 4k7 changed to 10k according to TPS82085SIL data sheet PG sink current rating.
  14. U47 STSAFE-TPM with corresponding circuits added.
  15. U19 and U37 LTM4638EY#PBF changed to TPS6287B15VA0WRZVR with corresponding circuits.
  16. R116 and net POR_B_R added.

REV06

PCN

2020-0405
  1. Revised PL_VCCINT power supply. PCB: revised routing and components placement.
  2. Added signal BG1 for DDP DDR4 IC. Added support of new packages. PCB: revised routing and components placement.
  3. R5 pulled up to 1.2V. R5 value changed to 49.9R.
  4. Added test points.
  5. Added MAC EEPROM U48. I2C bus PLL_SCL/SDA. Added pull up resistor to I2C bus.
  6. PCB - revised FPGA location. Package placed 1.5mm closer to connector J3.
  7. PCB - updated silkscreen. Added company address, CE and WEEE symbols.
  8. PCB - updated signal trace lengths.

29.11.2022

  9. Changed note near J2.97 and net PG_GT_L from "On board pull-up R" to "External pull-up R Required"

30.04.2025

10. MT: L1-L5, L7 (obsolete) changed to MPZ0603S121HT000

REV05

PCN
PCN
PCN
PCN
PCN

-04A
  1. R19 value was changed to 10K (was: 4K99) to set PS_MGTRAVCC 0.85V

REV04

PCN
PCN

-04
  1. Added resistors R65, R82, R86, R87 (240R) for each DDR4-chip for supporting DDP DDR4 chips
  2. Full library update
-03

-

REV03
-02-REV02
-01
  • Initial release

Hardware revision history

Document Change History

 Date

Revision

ContributorsDescription

  • Updated pictures - Main Components and Hardware Revision Number - to hardware revision 06
  • Hardware History table - Fixed visuals
2026-06-19

v.53

Kilian Jahn

  • Updated to hardware revision 06
  • Updated TRM template to 4.3.8

2024-09-24

v.50

John Hartfiel

  • Change default RAM size on key feature section
  • Typo and revision history update

2024-09-18

v.48

John Hartfiel

  • Review and Public Update

2023-10-13

v.44

ED 

  • Updated to new TRM style

2022-09-13

v.41Vadim Yunitski
  • Updated PG_PL pull-up resistor requirements
2021-09-07V.39John Hartfiel
  • Correction Power section
2021-05-17v.37John Hartfiel
  • Typo correction in DDR section
2021-03-11v.35Antti Lukats
  • Typo correction in PLL_RST
  • Add pin on power rails table
  • Correction MGT Lane assignment
  • Correction MGT CLK assignment

2019-01-27

v.30Martin Rohrmüller
  • Corrected clock connection to J2

2018-11-20

v.29

John Hartfiel
  • Notes for power supply

2018-08-27

v.27John Hartfiel
  • Typo correction SI5345 I2C address

2028-06-28

v.26John Hartfiel
  • Typo SI5348 B2B IOs + link correction

2017-11-13

v.24Ali Naseri
  • Updated B2B connector max. current rating per pin

2017-11-13

v.22
John Hartfiel
  • Rework B2B section
2017-10-20

v.21

Ali Naseri
  • Update links (pdf, documentation) to revision 4
  • ES silicon note removed
2017-08-28
v.15
John Hartfiel
  • Update section: Variants Currently In Production

2017-08-28v.14Jan Kumann
  • Block diagram changed.
  • SPI flash section fixed.
  • Few smaller improvements.
2017-08-15v.12Vitali Tsiukala
  • Changed signals count in the B2B connectors table
2017-08-15

v.11

John Hartfiel, Ali Naseri
  • PCB REV04 Initial release
  • Update boot mode section
2017-02-06v.1Jan Kumann
  • Initial document

--

all

  • --
Document change history.

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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.



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