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Overview

MicroBlaze Design with Linux example.

Refer to http://trenz.org/te0713-info for the current online version of this manual and other available documentation.

For directly getting started with the prebuilt files jump to the section Launch.

Key Features

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Design supports following carriers:

Additional HW Requirements:

Content

For general structure and of the reference design, see Project Delivery - AMD devices

Design Sources

Additional Sources

Prebuilt

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TE0713 "Test Board" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• AMD Development Tools#XilinxSoftware-BasicUserGuides
• Vivado Projects - TE Reference Design
• Project Delivery

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For current script limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   

   
   

   Code Block
   language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh
   ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):

   
   

2. Press 0 and enter to start "Module Selection Guide"
3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
4. Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
   

   • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

     Note
     Note: Select correct one, see also Vivado Board Part Flow

     
     

5. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

   Code Block
   language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
   TE::hw_build_design -export_prebuilt

   
   

   Info
   Using Vivado GUI is the same, except file export to prebuilt folder.

   
   

6. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
   • use TE Template from "<project folder>\os\petalinux"

   • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

   • The build images are located in the "<plnx-proj-root>/images/linux" directory

7. Configure the boot.scr file as needed, see Distro Boot with Boot.scr

8. Add Linux files (uboot.elf, image.ub, boot.scr) to prebuilt folder

   Info
   copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"

   
   

9. Generate Programming Files with Vitis

   Code Block
   language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
   TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

   
   

   Note
   TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

   
   

10. (Optional) BlockRam Firmware Update
    Copy "<project folder>\prebuilt\software\<short name>\spi_bootloader.elf" into  "<project folder>\firmware\microblaze_0\"

    1. Regenerate Vivado Project or Update Bitfile only with new "spi_bootloader.elf". "spi_bootloader.elf" is automatically rebuild and replaced in firmware folder after sw_run_vitis.

       Code Block
       language bash theme Midnight
       TE::hw_build_design -export_prebuilt TE::sw_run_vitis -all

       
       

Launch

Programming

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
2. Press 0 and enter to start "Module Selection Guide"
   1. Select assembly version
   2. Validate selection

   3. Select Create and open delivery binary folder

      Info
      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

      
      

QSPI-Boot mode

Option for u-boot.mcs on QSPI Flash.
(u-boot.mcs contains all files necessary to boot up linux)

1. Connect the USB cable(JTAG) and power supply on carrier with module

2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd".
   Enter the following TCL-Command into the TCL-Console inside Vivado to program the QSPI Flash.

   Code Block
   language py theme Midnight title run on Vivado TCL (Script programs u-boot.mcs on QSPI flash)
   TE::pr_program_flash -swapp u-boot

   
   

SD-Boot mode

Not used on this Example.

JTAG

Not used on this Example.

Usage

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)

3. Select QSPI as Boot Mode

   Info
   Note: See TRM of the Carrier, which is used.

   
   

   
   

4. Power On PCB and push the reset button if present on carrier.
   

   
   

   Expand
   title boot process
   1. FPGA Loads Bitfile from Flash, 2. SPI Bootloader from Bitfile Firmware loads U-Boot into DDR, 3. U-boot loads Linux from QSPI Flash into DDR Scroll Title anchor Figure_VHM1 title Boot process takes a while, please wait... Image RemovedImage Added

   
   

   
   

   
   

   
   

Linux

1. Open Serial Console (e.g. PuTTY)
   
   • Speed: 9600

   • select COM Port

     Info
     Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

     
     

2. Linux Console:
   

   petalinux login: root Password: root

   Code Block
   language bash theme Midnight

   
   

   Info
   Note: Wait until Linux boot finished

   
   

Vivado HW Manager

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)

• Monitoring:
  • MIG Calibration Done
  • Main Reset
  • MicroBlaze Reset

System Design - Vivado

Block Design

Constraints

FPGA Pin constraints can be found in the board files.

Basic module constraints

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design]
#
#
#

Software Design - Vitis

For Vitis project creation, follow instructions from:

Vitis

Application

Template location: ./sw_lib/sw_apps/

spi_bootloader

TE modified SPI Bootloader from Henrik Brix Andersen.

Bootloader to load app or second bootloader from flash into DDR.

Here it loads the u-boot.elf from QSPI-Flash to RAM. Hence u-boot.srec becomes redundant. 

Descriptions:

• Modified Files: bootloader.c
• Changes:
  
  • Change the SPI defines in the header
  • Add some reiteration in the frist spi read call

hello_te0713

Hello TE0713 is a Xilinx Hello World example as endless loop instead of one single console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate the file u-boot. srec(obsolete). Vivado is used to generate the file *.mcs

Software Design -  PetaLinux

For PetaLinux installation and  project creation, follow instructions from:

• PetaLinux KICKstart

Config

Start with petalinux-config or petalinux-config --get-hw-description

(Tipp: Search for Settings with shortcut "Shift"+"/")

Changes:

• SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART0_SIZE = 0x5E0000  (fpga)

• SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART1_SIZE = 0x400000  (boot)

• SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART2_SIZE = 0x20000    (bootenv)

• SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART3_SIZE = 0xA00000  0xF00000  (kernel)

  • (with this kernel flash address is 0xA00000 (fpga+boot+bootenv) and Kernel size 0xA000000xF00000)

U-Boot

Start with petalinux-config -c u-boot

Changes: (e.g. activate CONFIG via petalinux GUI like [*] Environment is not stored)

• CONFIG_ENV_IS_NOWHERE=y
• # CONFIG_ENV_IS_IN_SPI_FLASH is not set

Content of platform-top.h located in <plnx-proj-root>/project-spec/meta-user/recipes-bsp/u-boot/files:

#include <configs/microblaze-generic.h>
#include <configs/platform-auto.h>

#define CONFIG_SYS_BOOTM_LEN 0xF000000

Device Tree

Content of system-user.dtsi located in <petalinux project directory>/project-spec/meta-user\recipes-bsp\device-tree\file:

/include/ "system-conf.dtsi"
/ {
};

Kernel

Start with petalinux-config -c kernel

Changes:

• No changes.

Rootfs

Start with petalinux-config -c rootfs

Changes:

• # CONFIG_dropbear is not set

• # CONFIG_dropbear-dev is not set

• # CONFIG_dropbear-dbg is not set

• # CONFIG_package-group-core-ssh-dropbear is not set

• # CONFIG_packagegroup-core-ssh-dropbear-dev is not set

• # CONFIG_packagegroup-core-ssh-dropbear-dbg is not set

• # CONFIG_imagefeature-ssh-server-dropbear is not set

Applications

No additional application.

Additional Software

No additional software is needed.

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

Legal Notices