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Overview


MicroBlaze Design with Linux example.

Refer to http://trenz.org/te0713-info for the current online version of this manual and other available documentation.

For directly getting started with the prebuilt files jump to the section Launch.

Key Features

  • Vitis/Vivado 2021.2
  • PetaLinux
  • MIG
  • FLASH

Revision History

DateVivadoProject BuiltAuthorsDescription
2022-02-162021.2TE0713-test_board_noprebuilt-vivado_2021.2-build_11_20220216083114.zip
TE0713-test_board-vivado_2021.2-build_11_20220216083114.zip
Waldemar
Hanemann
  • new spi bootloader
    by Henrik Brix Andersen
  • adjusted offsets
2022-01-052021.2TE0713-test_board_noprebuilt-vivado_2021.2-build_6_20220105112236.zip
TE0713-test_board-vivado_2021.2-build_6_20220105112236.zip
Waldemar
Hanemann
  • 2021.2 update
  • added distroboot
2021-12-082020.2

TE0713-test_board_noprebuilt-vivado_2020.2-build_9_20211210090602.zip
TE0713-test_board-vivado_2020.2-build_9_20211210090545.zip

Waldemar
Hanemann

  • 2020.2 update
  • template style
2020-07-092019.2

TE0713-test_board_noprebuilt-vivado_2019.2-build_13_20200709071700.zip
TE0713-test_board-vivado_2019.2-build_13_20200709071613.zip

John Hartfiel
  • initial release
Design Revision History

Release Notes and Know Issues

IssuesDescriptionWorkaroundTo be fixed version
petalinux-build failed on 2020.2---activate "Networking support" in petalinux-config -c u-boot
  • implemented in vivado 2020.2
Known Issues

Requirements

Software

SoftwareVersionNote
Vitis2021.2needed, Vivado is included into Vitis installation
PetaLinux2021.2needed
Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0713-02-100-2c*100_2cREV02|REV011GB32MBNANANA
TE0713-02-200-2c200_2cREV02|REV011GB32MBNANANA

*used as reference

Hardware Modules

Design supports following carriers:

Carrier ModelNotes
TE0701
TE0703*
TE0705
TE0706
TEBA0841

*used as reference

Hardware Carrier

Additional HW Requirements:

Additional HardwareNotes
USB Cable for JTAG/UARTCheck Carrier Board and Programmer for correct typ
XMOD ProgrammerCarrier Board dependent, only if carrier has no own FTDI
Additional Hardware

Content

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

TypeLocationNotes
Vivado<project folder>/block_design
<project folder>/constraints
<project folder>/ip_lib
Vivado Project will be generated by TE Scripts
Vitis<project folder>/sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<project folder>/os/petalinuxPetaLinux template with current configuration
Design sources

Additional Sources

TypeLocationNotes
------
Additional design sources

Prebuilt

File

File-Extension

Description

BIT-File*.bitFPGA (PL Part) Configuration File
Boot Source*.scrDistro Boot file
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File

MCS-File

*.mcs

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

MMI-File

*.mmi

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

SREC-File

*.srec

Converted Software Application for MicroBlaze Processor Systems

Prebuilt files (only on ZIP with prebult content)

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Design Flow


Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For current script limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
    _create_win_setup.cmd/_create_linux_setup.sh
    ------------------------Set design paths----------------------------
    -- Run Design with: _create_win_setup
    -- Use Design Path: <absolute project path>
    --------------------------------------------------------------------
    -------------------------TE Reference Design---------------------------
    --------------------------------------------------------------------
    -- (0)  Module selection guide, project creation...prebuilt export...
    -- (1)  Create minimum setup of CMD-Files and exit Batch
    -- (2)  Create maximum setup of CMD-Files and exit Batch
    -- (3)  (internal only) Dev
    -- (4)  (internal only) Prod
    -- (c)  Go to CMD-File Generation (Manual setup)
    -- (d)  Go to Documentation (Web Documentation)
    -- (g)  Install Board Files from Xilinx Board Store (beta)
    -- (a)  Start design with unsupported Vivado Version (beta)
    -- (x)  Exit Batch (nothing is done!)
    ----
    Select (ex.:'0' for module selection guide):
  2. Press 0 and enter to start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
    • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

      Note: Select correct one, see also Vivado Board Part Flow

  5. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

    run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
    TE::hw_build_design -export_prebuilt

    Using Vivado GUI is the same, except file export to prebuilt folder.

  6. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
    • use TE Template from "<project folder>\os\petalinux"
    • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

    • The build images are located in the "<plnx-proj-root>/images/linux" directory

  7. Configure the boot.scr file as needed, see Distro Boot with Boot.scr
  8. Add Linux files (uboot.elf, image.ub, boot.scr) to prebuilt folder

    • copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"
  9. Generate Programming Files with Vitis

    run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
    TE::sw_run_vitis -all
    TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

    TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

  10. (Optional) BlockRam Firmware Update
    1. Copy "<project folder>\prebuilt\software\<short name>\spi_bootloader.elf" into  "<project folder>\firmware\microblaze_0\"

    2. Regenerate Vivado Project or Update Bitfile only with new "spi_bootloader.elf"

      TE::hw_build_design -export_prebuilt
      TE::sw_run_vitis -all

Launch


Programming

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select Create and open delivery binary folder

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

QSPI-Boot mode

Option for u-boot.mcs on QSPI Flash.
(u-boot.mcs contains all files necessary to boot up linux)

  1. Connect the USB cable(JTAG) and power supply on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd".
    Enter the following TCL-Command into the TCL-Console inside Vivado to program the QSPI Flash.

    run on Vivado TCL (Script programs u-boot.mcs on QSPI flash)
    TE::pr_program_flash -swapp u-boot
    

SD-Boot mode

Not used on this Example.

JTAG

Not used on this Example.


Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select QSPI as Boot Mode

    Note: See TRM of the Carrier, which is used.

  4. Power On PCB and push the reset button if present on carrier.

    1. FPGA Loads Bitfile from Flash,

    2. SPI Bootloader from Bitfile Firmware loads U-Boot into DDR,

    3. U-boot loads Linux from QSPI Flash into DDR


    Boot process takes a while, please wait...



Linux

  1. Open Serial Console (e.g. PuTTY)
    • Speed: 9600
    • select COM Port

      Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

  2. Linux Console:

    petalinux login: root
    Password: root

    Note: Wait until Linux boot finished

Vivado HW Manager

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)

  • Monitoring:
    • MIG Calibration Done
    • Main Reset
    • MicroBlaze Reset



Vivado Hardware-Manager

System Design - Vivado


Block Design

Block Design

Constraints

Basic module constraints

_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constraints

_i_bitgen.xdc
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design]
#
#
#

Software Design - Vitis


For Vitis project creation, follow instructions from:

Vitis

Application

Template location: ./sw_lib/sw_apps/

spi_bootloader

TE modified SPI Bootloader from Henrik Brix Andersen.

Bootloader to load app or second bootloader from flash into DDR.

Here it loads the u-boot.elf from QSPI-Flash to RAM. Hence u-boot.srec becomes redundant.

Descriptions:

  • Modified Files: bootloader.c
  • Changes:
    • Change the SPI defines in the header
    • Add some reiteration in the frist spi read call

hello_te0713

Hello TE0713 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate the file u-boot.srec(obsolete). Vivado is used to generate the file *.mcs

Software Design -  PetaLinux


For PetaLinux installation and  project creation, follow instructions from:

Config

Start with petalinux-config or petalinux-config --get-hw-description

(Tipp: Search for Settings with shortcut "Shift"+"/")

Changes:

  • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART0_SIZE = 0x5E0000  (fpga)

  • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART1_SIZE = 0x400000  (boot)

  • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART2_SIZE = 0x20000    (bootenv)

  • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART3_SIZE = 0xA00000  (kernel)

    • (with this kernel flash address is 0xA00000 (fpga+boot+bootenv) and Kernel size 0xA00000)

U-Boot

Start with petalinux-config -c u-boot

Changes: (e.g. activate CONFIG via petalinux GUI like [*] Environment is not stored)

  • CONFIG_ENV_IS_NOWHERE=y
  • # CONFIG_ENV_IS_IN_SPI_FLASH is not set

Content of platform-top.h located in <plnx-proj-root>/project-spec/meta-user/recipes-bsp/u-boot/files:

#include <configs/microblaze-generic.h>
#include <configs/platform-auto.h>

#define CONFIG_SYS_BOOTM_LEN 0xF000000

Device Tree

Content of system-user.dtsi located in <petalinux project directory>/project-spec/meta-user\recipes-bsp\device-tree\file:

/include/ "system-conf.dtsi"
/ {
};

Kernel

Start with petalinux-config -c kernel

Changes:

  • No changes.

Rootfs

Start with petalinux-config -c rootfs

Changes:

  • # CONFIG_dropbear is not set

  • # CONFIG_dropbear-dev is not set

  • # CONFIG_dropbear-dbg is not set

  • # CONFIG_package-group-core-ssh-dropbear is not set

  • # CONFIG_packagegroup-core-ssh-dropbear-dev is not set

  • # CONFIG_packagegroup-core-ssh-dropbear-dbg is not set

  • # CONFIG_imagefeature-ssh-server-dropbear is not set


Applications

No additional application.

Additional Software

No additional software is needed.

Appx. A: Change History and Legal Notices


Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument Revision

Authors

Description

  • new spi bootloader
    by Henrik Brix Andersen
  • adjusted offsets
2022-01-05


v.5


Waldemar Hanemann


  • 2021.2 release
  • added distroboot
2021-12-08v.3Waldemar Hanemann
  • 2020.2 release
  • petalinux workarounds
2020-07-09


v.1


John Hartfiel


  • 2019.2 initial release
--all--
Document change history.

Legal Notices

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Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

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Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

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REACH, RoHS and WEEE

REACH

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RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

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