Page History

4 GTH lanes

(4 RX / 4 TX)

B228_RX3_P, B228_RX3_N, pins J1-51, J1-53
B228_TX3_P, B228_TX3_N, pins J1-50, J1-52

B228_RX2_P, B228_RX2_N, pins J1-57, J1-59
B228_TX2_P, B228_TX2_N, pins J1-56, J1-58

B228_RX1_P, B228_RX1_N, pins J1-63, J1-65
B228_TX1_P, B228_TX1_N, pins J1-62, J1-63

B228_RX0_P, B228_RX0_N, pins J1-69, J1-71
B228_TX0_P, B228_TX0_N, pins J1-68, J1-70

1 reference clock signal (B228_CLK0) from B2B connector
J3 (pins J3-60, J3-62) to bank's pins R8/R7

1 reference clock signal (B228_CLK1) from programmable
PLL clock generator U5 to bank's pins N8/N7

4 GTH lanes

(4 RX / 4 TX)

B229_RX3_P, B229_RX3_N, pins J1-27, J1-29
B229_TX3_P, B229_TX3_N, pins J1-26, J1-28

B229_RX2_P, B229_RX2_N, pins J1-33, J1-35
B229_TX2_P, B229_TX2_N, pins J1-32, J1-34

B229_RX1_P, B229_RX1_N, pins J1-39, J1-41
B229_TX1_P, B229_TX1_N, pins J1-38, J1-40

B229_RX0_P, B229_RX0_N, pins J1-45, J1-47
B229_TX0_P, B229_TX0_N, pins J1-44, J1-46

1 reference clock signal (B229_CLK0) from B2B connector
J3 (pins J3-65, J3-67) to bank's pins L8/L7

1 reference clock signal (B229_CLK1) from programmable
PLL clock generator U5 to bank's pins J8/J7

4 GTH lanes

(4 RX / 4 TX)

B230_RX3_P, B230_RX3_N, pins J1-3, J1-5
B230_TX3_P, B230_TX3_N, pins J1-2, J1-4

B230_RX2_P, B230_RX2_N, pins J1-9, J1-11
B230_TX2_P, B230_TX2_N, pins J1-8, J1-10

B230_RX1_P, B230_RX1_N, pins J1-15, J1-17
B230_TX1_P, B230_TX1_N, pins J1-14, J1-16

B230_RX0_P, B230_RX0_N, pins J1-21, J1-23
B230_TX0_P, B230_TX0_N, pins J1-20, J1-22

1 reference clock signal (B230_CLK1) from B2B connector
J3 (pins J3-59, J3-61) to bank's pins G8E8/G7E7

1 reference clock signal (B230_CLK0) from programmable
PLL clock generator U5 to bank's pins E8G8/E7G7

4 GTH lanes

(4 RX / 4 TX)

B128_RX3_N, B128_RX3_P, pins J2-28, J2-30
B128_TX3_N, B128_TX3_P, pins J2-25, J2-27

B128_RX2_N, B128_RX2_P, pins J2-34, J2-36
B128_TX2_N, B128_TX2_P, pins J2-31, J2-33

B128_RX1_N, B128_RX1_P, pins J2-40, J2-42
B128_TX1_N, B128_TX1_P, pins J2-37, J2-39

B128_RX0_N, B128_RX0_P, pins J2-46, J2-48
B128_TX0_N, B128_TX0_P, pins J2-43, J2-45

1 reference clock signal (B128_CLK1) from B2B connector
J2 (pins J2-22, J2-24) to bank's pins D25/D26

1 reference clock signal (B128_CLK0) from programmable
PLL clock generator U5 to bank's pins F25/F26

4 GTR lanes

(4 RX / 4 TX)

B505_RX3_N, B505_RX3_P, pins J2-52, J2-54
B505_TX3_N, B505_TX3_P, pins J2-49, J2-51

B505_RX2_N, B505_RX2_P, pins J2-58, J2-60
B505_TX2_N, B505_TX2_P, pins J2-55, J2-57

B505_RX1_N, B505_RX1_P, pins J2-64, J2-66
B505_TX1_N, B505_TX1_P, pins J2-61, J2-63

B505_RX0_N, B505_RX0_P, pins J2-70, J2-72
B505_TX0_N, B505_TX0_P, pins J2-67, J2-69

2 reference clock signals (B505_CLK0, B505_CLK1) from B2B connector
J2 (pins J2-10/J2-12, J2-16/J2-18) to bank's pins P25/P26, M25/M26

2 reference clock signal (B505_CLK2, B505_CLK3) from programmable
PLL clock generator U5 to bank's pins K25/K26, H25/H26

• typo correction in PLL_RST
• add pin on power rails table
• correction MGT Lane assignment
• correction MGT CLK assignment

07 Jan 2019

• Corrected clock connection to J2

20 Nov 2018

v.29

• Notes for power supply

27 Aug 2018

• typo correction SI5345 I2C address

28 Jun 2018

• typo SI5348 B2B IOs + link correction

13 Nov 2017

• updated B2B connector max. current rating per pin

• rework B2B section

v.21

• Update links (pdf, documentation) to revision 4
• ES silicon note removed

• Update section: Variants Currently In Production

• Block diagram changed.
• SPI flash section fixed.
• Few smaller improvements.

• PCB REV04 Initial release
• update boot mode section